D&R News Alert
May 8th, 2025
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Welcome to the issue of May 8th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry News
■ Enabling the next generation of smart glasses
Design Platform
■ CELUS Design Platform integrates with Cadence’s OrCAD X Platform
■ Multi-talented magnetic field sensor: Robust position, angle and current measurement with the same chip
Products
 ❖ UniLC Semiconductor - SoC Design Service

Join Synopsys Webinar “Application-Specific Processors (ASIPs) for Wireless Communication SoCs”
Synopsys Date: May 21, 2025 | Time: 7 am PT / 4 pm CEST
Gain insights into how ASIPs can enhance your 5G SoC designs.
 Register now to secure your spot! >>

Analog IP
■ Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications
Interface IP
■ MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications
■ MIPI in FPGAs for mobile-influenced devices - By Mixel
■ Keysight Expands USB Standards Support in System Designer for USB
Sofics High voltage tolerant I/O

• Enable high voltage operation, beyond foundry IO levels.
• 1.8V GPIO in 4nm based on 1.2V transistors

Info about Sofics >>

RISC-V
■ Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
■ Andes Voyager RISC-V Micro-ATX Board Seeing Patches For Mainline Linux Support
■ Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris
Products
 ❖ Cervell - All-In-One RISC-V NPU

Artificial Intellgence
■ Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor
■ Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
■ Quadric’s Chimera GPNPU Named Best Edge AI Processor IP by Edge AI and Vision Alliance
■ The Democratization of AI Computing: Building an Inclusive Semiconductor Future
■ Connected AI is More Than the Sum of its Parts - Blog by Ceva, Inc.
Products
 ❖ Tensilica NeuroEdge AI Co-Processor
❖ Quadric General Purpose Neural Processing Unit (NPU)

Movellus
Aeonic Insight™ PDN IQ
• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle
• Cross-trigger matrix interface for sophisticated tracing, including look-behind capability
• Process portable
Learn More >>

Audio/Video
■ Xylon Introduces Xylon ISP Studio
Products
 ❖ XYLON ISP Studio

Automotive
■ Boss Semiconductor's CEO Park Jae-hong aims to disrupt Qualcomm's automotive chip dominance
■ Xylon at ADAS&AVT Expo Europe 2025
Products
 ❖ Virtual ECU / Software Defined Vehicles (SDV)
❖ ADAS Validation & Verification

Security
■ Understanding Lifecycle Management for Secure Embedded Systems - Secure-IC blog
Quantum Computing
■ Synopsys slides into design enablement role in quantum computing
Green Electronics
■ FTD solutions partners with CEA-Leti to improve semiconductor manufacturing water management
Partner News
■ Agile Analog appoints CEO to drive growth
■ Cadence’s Nimish Modi to Present at Needham Conference
Business News
■ AMD Reportedly Drops Samsung Foundry in Favor of TSMC’s 4nm Production in Arizona
■ Global Semiconductor Sales Increase 18.8% in Q1 2025 Compared to Q1 2024; March 2025 Sales up 1.8% Month-to-Month





What they said at
IP SoC Silicon Valley 25

Interview with Mahesh Tirupattur - CEO - Analog Bits Inc.

Interview with Floriberto Lima - CEO - SiliconGate

Interview with Farzad Zarrinfar - Senior VP of Sales and Marketing - Innosilicon

Interview with Ook Kim - CEO - 4lynx, Inc.

Interview with Hoyeon Jeon - CEO - ITDA Semiconductor Co., Ltd.

Welcome to the IP soc community
Gabrièle Saucier, CEO & Founder, Design and Reuse

Did RISC-V Change the Design World?
Marc Evans, Director of Business Development & Marketing, Andes Technology Corp.

Revolutionizing Semiconductor Design with Smart NoC IP: Unprecedented Productivity Improvements and Quality of Results
Guillaume Boillet, Sr. Director Strategic Marketing, Arteris IP

Scaling AI Infrastructures for the Future with Next-Gen Interconnects
Aparna Tarde, Sr. Staff Technical Product Manager, Synopsys, Inc.

Unleashing the Performance of AI Training with HBM4
Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Foundry

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