1851 1.0

TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1852 1.0

TSMC CLN40G 40nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1853 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1854 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1855 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1856 1.0

TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1857 1.0

Always-on Voice Activity Detection interfacing with analog microphones The WT-a-HD.03 is a mixed analog/digital Virtual Component (ViC) containing a Voice Activity Detection (VAD) engine for ultra low power applications....

1858 1.0

TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1859 1.0

TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1860 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1861 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1862 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1863 1.0

TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1864 1.0

TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1865 1.0

TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1866 1.0

TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1867 1.0

TSMC CLN65GP 65nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1868 1.0

TSMC CLN65LP 65nm DDR DLL - 164MHz-820MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1869 1.0

TSMC CLN80GC 80nm DDR DLL - 196MHz-980MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1870 1.0

TSMC CLN80GT 80nm DDR DLL - 335MHz-1675MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1871 1.0

TSMC CLN80HS 80nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1872 1.0

TSMC CLN90G 90nm DDR DLL - 196MHz-980MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1873 1.0

TSMC CLN90GOD 90nm DDR DLL - 272MHz-1360MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1874 1.0

TSMC CLN90GT 90nm DDR DLL - 335MHz-1675MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1875 1.0

TSMC CLN90LP 90nm DDR DLL - 164MHz-820MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1876 1.0

UMC L130LL 130nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1877 1.0

UMC L130LL 130nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1878 1.0

UMC L130LL 130nm Deskew PLL - 30MHz-150MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1879 1.0

UMC L130LL 130nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1880 1.0

UMC L130LL 130nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1881 1.0

UMC L130LL 130nm Clock Generator PLL - 30MHz-150MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1882 1.0

UMC L130LL 130nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1883 1.0

UMC L130LL 130nm Spread Spectrum PLL - 60MHz-300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1884 1.0

UMC L130LL 130nm Spread Spectrum PLL - 30MHz-150MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1885 1.0

UMC L130LL 130nm DDR DLL - 32MHz-160MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1886 1.0

UMC L130LL 130nm DDR DLL - 24MHz-120MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1887 1.0

UMC L65LL 65nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1888 1.0

UMC L65LL 65nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1889 1.0

UMC L65LL 65nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1890 1.0

UMC L65SP 65nm Deskew PLL - 520MHz-2600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1891 1.0

UMC L65SP 65nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1892 1.0

UMC L65SP 65nm Deskew PLL - 130MHz-650MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1893 1.0

UMC L65LL 65nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1894 1.0

UMC L65LL 65nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1895 1.0

UMC L65LL 65nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1896 1.0

UMC L65SP 65nm Clock Generator PLL - 520MHz-2600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1897 1.0

UMC L65SP 65nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1898 1.0

UMC L65SP 65nm Clock Generator PLL - 130MHz-650MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1899 1.0

UMC L65LL 65nm Spread Spectrum PLL - 240MHz-1200MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1900 1.0

UMC L65LL 65nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...