2851 0.118

Band Gap IP, VBG=1.23V, UMC 0.35um process The FXBG010H80A is a complete bandgap voltage reference circuit with low temperature coefficient, and high power supply rejection ratio with output vo...

2852 0.118

Linear Regulator IP, Output: 5V/50mA, UMC 0.35um process 5V with 50mA driving capability, Istb=124uA Linear Regulator, UMC 0.35um Logic process....

2853 0.118

Power on Reset IP, Input: 3.3V, UMC 0.35um process Vrr=2.5V Vfr=2.3V, VCC=3.3V, Ivcc=18uA, Power On Reset, UMC 0.35um Logic process....

2854 0.118

Linear Regulator IP, Output: 5V/150mA, UMC 0.35um process 5V with 150mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process....

2855 0.118

Voltage Detector IP, Vdet: 2.55V, UMC 0.35um process Vdet=2.55V Vhys=0.05V, VCC=3.3V, Ivcc=35uA, UMC 0.35um Logic process....

2856 0.118

A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process 10-Bit 300KSPS single End Analog-to-Digital converter, UMC 0.35um Logic process....

2857 0.118

RC Oscillator IP, Output: 27.5MHz, UMC 0.35um Logic process 27.5MHz trimmable RC Oscillator, UMC 0.35um Logic process....

2858 0.118

DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....

2859 0.118

RC Oscillator IP, Output: 10KHz, UMC 0.35um Logic process Sub-low current with external-C, frequency 10KHz, VCCA=2.0V~3.3V, Ivcca<10uA....

2860 0.118

Linear Regulator IP, Output: 5V/70mA, UMC 0.35um Logic process 5V with 70mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process....

2861 0.118

PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process....

2862 0.118

Voltage Detector IP, Vdet: 3.3V, UMC 0.5um process 5V/3.3V detector VDT, UMC 0.5um Logic process....

2863 0.118

Power on Reset IP, Input: 5V, UMC 0.5um process Vrr=3.4V Vfr=3.0V, VCC=5V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process....

2864 0.118

Power on Reset IP, Input: 3.3V, UMC 0.5um process Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process....

2865 0.118

Power on Reset IP, Input: 3.3V, UMC 0.5um process Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, L type IO, Power On Reset, UMC 0.5um Logic process low voltage....

2866 0.118

An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process. An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....

2867 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process. Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

2868 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

2869 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process . Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

2870 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

2871 0.118

Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process. Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process....

2872 0.118

Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process. Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process....

2873 0.118

Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process. Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process....

2874 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process. Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

2875 0.118

Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40n...

2876 0.118

Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm ...

2877 0.118

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Pro...

2878 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...

2879 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...

2880 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...

2881 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...

2882 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...

2883 0.118

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Pr...

2884 0.118

1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process 1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process...

2885 0.118

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

2886 0.118

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%. UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%....

2887 0.118

Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process....

2888 0.118

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...

2889 0.118

Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process. Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process....

2890 0.118

1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process 1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process...

2891 0.118

Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process...

2892 0.118

XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process...

2893 0.118

Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process...

2894 0.118

NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process. NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process....

2895 0.118

Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process...

2896 0.118

internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process...

2897 0.118

NO External-R ,frequency 32.768MHz , Oscillator . Input 0.9V+/-10% ,1.2V+/-10% ; UMC 55nm ULP process. NO External-R ,frequency 32.768MHz , Oscillator . Input 0.9V+/-10% ,1.2V+/-10% ; UMC 55nm ULP process....

2898 0.118

Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process. Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process....

2899 0.118

Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process...

2900 0.118

NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process. NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process....