3801 0.0

UMC L40LP 40nm Deskew PLL - 150MHz-750MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3802 0.0

UMC L40LP 40nm Deskew PLL - 75MHz-375MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3803 0.0

UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3804 0.0

40 mA LDO voltage regulator (3.3/5.0V to 1.8V) 180TSMC_LDO_20 is LDO to convert IO voltage 3.0V÷5.5V to 1.8V and designed to supply integrated circuits with stable and precise voltage with load up ...

3805 0.0

On-Chip IO to Core Voltage Buck Regulator The OT1153 series on-chip regulators allow for efficient on-chip conversion of IO voltages to Core voltages. E.g. 3.3V to 1.2V with only one external ...

3806 0.0

GF L013N 130nm DDR DLL - 68MHz-340MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3807 0.0

TSMC CLN6FF 6nm Spread Spectrum PLL - 175MHz-875MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3808 0.0

UMC L55LP 55nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3809 0.0

PVT Sensor - TSMC 16 FFC 1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...

3810 0.0

PVT Sensor - TSMC 12 FFC 1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...

3811 0.0

PVT Sensor - TSMC 28 HPC+ 1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...

3812 0.0

PVT Sensor - TSMC 40 1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...

3813 0.0

Low Dropout (LDO) Capless Regulator 250mA - TSMC 28 HPC+ 1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide ...

3814 0.0

Low Dropout (LDO) Capless Regulator 250mA - TSMC 40 1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide ...

3815 0.0

16bit 100Ksps Sigma Delta ADC in 130nm~22nm This IP include a PGA and a delta-sigma ADC, can be used in various sensor measurement....

3816 0.0

16bit 3Msps Sigma Delta ADC in 130nm~22nm This IP is an 16-bit resolution sigma-delta ADC, can be used in various sensor measurement....

3817 0.0

12bit R2R DAC This IP is a 12-bit resolution, 1MHz convert rate R2R DAC on 180nm~ 12nm process. The internal DAC includes data latch circuits, R2R ladder and output...

3818 0.0

100nA Ultra-low Power LDO in 110nm~12nm The LDO IP supports various input voltage ranges include 1.90V~3.60V, 1.90V~5.50V and so on. The typical output voltage of this LDO can be configratio...

3819 0.0

UMC L55LP 55nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3820 0.0

UMC L65LP 65nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3821 0.0

UMC L65LP 65nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3822 0.0

UMC L65LP 65nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3823 0.0

GF L28HPP 28nm Deskew PLL - 700MHz-3500MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3824 0.0

GF L28HPP 28nm Deskew PLL - 350MHz-1750MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3825 0.0

12-bit, 9.2 GSPS Analog-to-Digital Converter The A12B9G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a time-interleaved successive a...

3826 0.0

11-bit, 5 GSPS Analog-to-Digital Converter The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a hybrid successive approxima...

3827 0.0

12-bit, 200 MSPS Analog-to-Digital Converter IP Block The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block. It is a hybrid successive approximatio...

3828 0.0

GF L28HPP 28nm Deskew PLL - 175MHz-875MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3829 0.0

GF L28SLP 28nm Deskew PLL - 440MHz-2200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3830 0.0

GF L28SLP 28nm Deskew PLL - 220MHz-1100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3831 0.0

GF L28SLP 28nm Deskew PLL - 110MHz-550MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3832 0.0

GF L55G 55nm Deskew PLL - 360MHz-1800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3833 0.0

GF L55G 55nm Deskew PLL - 180MHz-900MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3834 0.0

GF L55G 55nm Deskew PLL - 90MHz-450MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3835 0.0

GF L55LP 55nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3836 0.0

GF L55LP 55nm Deskew PLL - 160MHz-800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3837 0.0

RF IO Pad Set The RF libraries include analog signal pads and ESD protection components for RF applications. Analog / RF cells * Low voltage LNA input pad (1....

3838 0.0

3.3V 100MHz Oscillator IO Inline Pad Set The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell. An adapter cell is included to utilize this oscillator with ...

3839 0.0

GF L55LP 55nm Deskew PLL - 80MHz-400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3840 0.0

GF L55LPE 55nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3841 0.0

GF L55LPE 55nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3842 0.0

GF L55LPE 55nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3843 0.0

TSMC CLN20SOC 20nm General Purpose PLL - 350MHz-1750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

3844 0.0

130kHz Internal Oscillator - Low voltage (1V), Low Power (160nW@130kHz) LFoundry (SMIC) 0.15 μm This macro-cell is a general purpose, ultra low power internal oscillator core designed for LFoundry 0.15µm LF150 CMOS technology STD (Standard) and L...

3845 0.0

Low-Power 10-bit SAR ADC - 10 bits, 240kSPS, 8 multiplexed inputs LFoundry 0.15 μm This macro-cell is a general purpose, 10-bit, 240kSPS, 8-multiplexed input Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) c...

3846 0.0

600mV Sub-BG Voltage Reference 600mV Sub-BG Voltage reference, Vdd=1V, Idd=80uA...

3847 0.0

5GHz RF Buffer 5GHz RF Buffer, Vdd=800mV, Idd=6mA...

3848 0.0

80GHz Amplitude detector 80GHz Amplitude Detector, Programmable treshold 100-450mV, 1Bit output...

3849 0.0

RF Counter, 8b RF Counter, 8b, up to 10GHz, Idd=600uA...

3850 0.0

Resistive DAC, 10b Resistive DAC, 10bit, Vdd=800mV, IDD=1.8mA...