1 20.0

LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

2 10.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC PLUS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

3 2.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF-NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

4 0.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

5 10.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

6 10.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

7 20.0

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

8 8.0

IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...

9 8.0

TSMC CLN16FFGL+ HBM PHY IP This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. Th...

10 8.0

TSMC CLN5FF HBM PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

11 8.0

TSMC CLN7FF HBM2E PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

12 20.0

LPDDR5/4x/4 PHY IP for Samsung 14LPU OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

13 20.0

LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

14 0.0

HBM3 PHY IP on TSMC N5 The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

15 10.0

DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...

16 10.0

SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

17 3.0

1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16nm 16nm & 12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C / SMBUS open-drain cell, 5V OTP cell, 1.8V & 3.3V analog cells, an...

18 1.0

MCR DDR5 PHY The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM...

19 0.0

TSMC CLN7FF 7nm LPDDR5 PHY - 6400Mbps The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...

20 28.0

LPDDR4x/5 Secondary/Slave (memory side!) PHY This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/L...

21 1.0

GDDR6X/6 Combo PHY&Controller Innosilicon GDDR6/6X Combo IP is fully compliant to the JEDEC GDDR6/6X standard, supporting up to 16Gbps per pin for PAM2 GDDR6 and 21Gbps for PAM4 GD...

22 0.0

ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL set...

23 0.0

DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP) This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throughput. The DDR IP is c...

24 0.0

DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+) The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ p...

25 0.0

DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+) This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput. The PHY IP is silicon proven...

26 0.0

DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+) The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps and DDR4 DRAM speeds...

27 0.0

DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP) The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps and DDR2 DRAM speeds ...

28 0.0

ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+) ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL se...

29 0.0

DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC) The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput. The PHY IP is compliant with the latest JEDEC standar...

30 0.0

DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+) The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ ...

31 50.0

DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC) The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog s...

32 0.118

Single Port SRAM Compiler IP, UMC 0.11um HS/AE process UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process 1.41um2 Cell Single Port SRAM compiler....

33 0.118

Single Port SRAM Compiler IP, UMC 0.11um LL/AE process UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process Single Port SRAM compiler with 141-Bit cell....

34 0.118

Single Port SRAM Compiler IP, UMC 0.11um LL process UMC 0.11um AE/LL eFlash Single Port SRAM....

35 0.118

Single Port SRAM Compiler IP, UMC 0.11um SP/AE process UMC 0.11um SP/AE Logic process Synchronous Single Port SRAM memory compiler with 1.41um2-Bit cell....

36 0.118

Single Port SRAM Compiler IP, UMC 0.11um HV process UMC 0.11um HV process 1.35um2 Single Port SRAM compiler....

37 0.118

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous, UMC 0.18um eFlash/G2 process UMC 0.18um eFlash process GII 4.0um2 Single Port SRAM compiler....

38 0.118

Single Port SRAM Compiler IP, 4.0um2 bit cells, High density, Low Power, UMC 0.18um LL process UMC 0.18um Logic process high density, Low Power, mini area, Single Port SRAM compiler....

39 0.118

Single Port SRAM Compiler IP, UMC 40nm LP process UMC 40nm LP 303HVT cell peripheral LVT....

40 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process UMC 40nm LP Logic process Ultra high speed Single Port SRAM memory compiler with Redundancy....

41 0.118

Single Port SRAM Compiler IP, UMC 40nm LP process UMC 40nm LP/HVT Logic process with 6TSRAM (0.242 mm2) Single Port SRAM memory compiler....

42 0.118

Single Port SRAM Compiler IP, UMC 40nm LP process UMC 40nm LP Logic process Single Port SRAM compiler with LVT peripheral....

43 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process UMC 40nm LP Logic process Single Port SRAM memory compiler with row redundancy....

44 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process UMC 40nm LP Logic process Single Port SRAM compiler LVT with row redundancy....

45 0.118

Single Port SRAM Compiler IP, UMC 40nm LP process UMC 40nm LP 303RVT cell peripheral LVT....

46 0.118

Single Port SRAM Compiler IP, UMC 55nm CIS process UMC 55nm CMOS Image Sensor 1P3M process Single Port SRAM memory compiler with peripheral HVT....

47 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process UMC 55 eHV process Single Port SRAM memory compiler with row Redundancy....

48 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process UMC 55nm eHV Low Power Low-K process synchronous high density, Single Port SRAM compiler with row redundancy option....

49 0.118

Single Port SRAM Compiler IP, UMC 55nm LP process UMC 55nm LP Low-K Logic process Synchronous Single Port SRAM memory compiler....

50 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process UMC 55nm LP Low-K Logic process Synchronous Single Port SRAM memory compiler with redundancy feature....