Design & Reuse
DDR (630)
eMMC (18)
Flash Controller (8)
HBM (30)
Mobile SDR Controller (4)
NAND Flash (35)
NVM Express (21)
ONFI Controller (4)
SD (12)
SDIO Controller (3)
SDRAM Controller (107)
SRAM Controller (3)
Other (21)
896 IP
51
25.0
HBM2E PHY V2 in TSMC (N7, N6, N5)
The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking AS...
52
20.0
LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
53
20.0
LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
54
20.0
LPDDR5/4x/4 PHY IP for Samsung 14LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
55
20.0
LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
56
20.0
112Gbps Serdes USR & XSR
With sophisticated architecture and advanced technology, KNL multi-mode D2D transceiver IP with PMA and PCS layer is designed for low power and high p...
57
20.0
Combo SerDes PHY
With sophisticated architecture and advanced technology, KNiulink multi-mode transceiver IP with PMA and PCS layer is designed for low power and high ...
58
20.0
xSPI Flash Memory Controller
The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directl...
59
20.0
32/64-bit PC133 SDRAM Controller
The 32/64-bit PC133 SDRAM Controller” controller handles PC133 SDRAM compatible memory devices attached to a 32 or 64 bit wide data bus. The cont...
60
20.0
LPDDR4x/4 PHY IP for 22nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
61
20.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
62
20.0
LPDDR5X/5/4X/4 combo PHY at 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
63
20.0
CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with mi...
64
20.0
UHS-II PHY
Silicon Library's world-first silicon proven UHS-II PHY supporting 1.56Gbps speed is available in various fabs/nodes, including TSMC6/12/40/85, GF28, ...
65
20.0
HBM3 PHY (Hard 1) in TSMC (N6, N5)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
66
20.0
HBM3 PHY in TSMC (N5, N6, N7)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
67
20.0
LPDDR4 multiPHY V2 in GF (22nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
68
20.0
LPDDR4X multiPHY in Samsung (14nm, 11nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
69
20.0
LPDDR4X multiPHY in GF (14nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
70
20.0
LPDDR4X multiPHY Plus in GF (12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
71
20.0
LPDDR5/4/4X PHY in GF (12nm)
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...
72
20.0
LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...
73
20.0
LPDDR5X/5/4X PHY in Samsung (SF4X, SF2)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
74
20.0
eMMC 5.1 Host Controller
The eMMC 5.1 Host Controller IP from Arasan Chip Systems is a highly integrated host controller IP solution. This IP handles all of the timing and ...
75
15.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
76
15.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
77
15.0
HBM3E Controller
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards...
78
15.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
79
14.0
NAND Flash Controller
Cadence IP Controller for ONFI NAND and Toggle NAND NAND Flash memory is widely used for data storage in computers and multiple consumer and enterpri...
80
14.0
Denali High-Speed DDR PHY for UMC
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area Developed by experienced ...
81
14.0
Denali Controller for DDR
LPDDR5/4X/4/3 and DDR5/4/3L/3, to 6400Mbps and beyond The Cadence Denali Controller IP for LPDDR5/4X/4/3 and DDR5/4/3L/3 provides low latency and up ...
82
14.0
GDDR6 PHY for Samsung
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
83
14.0
Denali Controller for GDDR6
GDDR6 devices to 16Gbps, 18Gbps, 20Gbps, and beyond The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwi...
84
14.0
Denali DDR PHY for TSMC
LPDDR4/3, DDR4/3/3L, up to 4266Mbps The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful prede...
85
14.0
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration in 40nm LL...
86
14.0
DDR34/LPDDR34 PHY - 28HK
B28HKDDRPHY-D34LP34 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-3B(LPDDR3), JESD209-4A (LPDDR4), DFI3.1 specification and delivers an...
87
14.0
DDR34/LPDDR23 PHY - 40LL
B40LLDDRPHY-D34LP23 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an u...
88
14.0
DDR3/LPDDR23 PHY - 55LL
B55LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combinat...
89
14.0
DDR3/LPDDR23 PHY - 65LL
B65LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combinat...
90
11.0
HBM3 PHY & Controller
SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HB...
91
11.0
DDR5/4 PHY & Controller
DDR5/4 PHY & Controller...
92
11.0
LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard...
93
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
94
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
95
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
96
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...
97
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
98
10.0
Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides adva...
99
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
100
10.0
Universal Multiport Memory Controller - LPDDR 3/2 Controller
Mobiveil's UMMC LPDDR3/2 Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption s...