601 0.0

DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC) The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput. The PHY IP is compliant with the latest JEDEC standar...

602 0.0

DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+) The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ ...

603 0.0

3rd Generation Software Defined Radio RF IP This is the 3rd Generation SDR RF IP that supports 1x1 and a frequency ranging from 100MHz to 2.6 GHz, which is currently in TSMC 40nm. The SDR Gen.3 ...

604 0.0

4th Generation Software Defined Radio RF IP This is the 4th Generation SDR RF IP that would support 2x2 and a frequency ranging from 200MHz to 7.3GHz with a support of up to 120MHz Bandwidth. Th...

605 0.0

Up to 50% main memory bandwidth acceleration The Ziptilion Bandwidth IP accelertes the main memory bandwidth with up to 50%. The IP core packages a novel and proprietary technology that accelerat...

606 0.0

high performance and low power With sophisticated architecture and advanced technology, KNiulink provide DDR5 with high performance and low power. In advanced process nodes, KNiuli...

607 0.0

DDR4/LPDDR4/LPDDR4X PHY M31 LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for ASICS, ASSPs, SOC an...

608 0.0

Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption R-Stratus-LPRR is an updated release of cache controller for MCU based on Non Volatile Memories (NVM) like eFlash or EEPROM. R-Stratus LPRR update con...

609 0.0

LPDDR5/4/4X Controller with Inline Memory Encryption (IME) Security Module SynopsysLPDDR5/4/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LP...

610 0.0

LPDDR4/ DDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+) The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ ...

611 0.0

DDR Memory Controller IP for low power and high reliability DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Specification Compliant...

612 0.0

DDR2 SDRAM Controller IP DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification and DFI-version 2.0 or higher Specification Compl...

613 0.0

DDR3 SDRAM Controller IP with advance feautures package DDR3 interface provides full support for the DDR3 interface, compatible with JESD79-3F specification and DFI-version 2.0 or higher Specification Compl...

614 0.0

DDR3L Memory Controller IP optimized for low latency DDR3L interface provides full support for the DDR3L interface, compatible with DDR3L protocol standard of 8GB_DDR3L and DFI-version 3.1 or higher Spec...

615 0.0

DDR4 Memory Controller IP with high performance DDR4 is full-featured, easy-to-use, synthesizable design, compatible with DDR4 JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D (...

616 0.0

DDR5 Memory Controller IP with Advanced Feautures DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 Rev1.40 (Draft) specification and DFI-version 5.0...

617 0.0

HBM3 PHY IP for TSMC N4 The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

618 0.0

LPDDR5 IP - High performance and low power With sophisticated architecture and advanced technology, KNiulink provide LPDDR5 with high performance and low power. In advanced process nodes, KNiu...

619 0.0

DDR5/4 Memory PHY for TSMC N7 Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 PH...

620 0.0

DDR5 Memory PHY for TSMC N5P Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PHY ...

621 0.0

DDR5 Memory PHY for TSMC N4P Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PHY ...

622 0.0

DDR5 Memory PHY for TSMC N3P Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PHY ...

623 0.0

DDR5 Memory PHY for Samsung SF5A Automotive Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PHY ...

624 0.0

DDR5/4 Memory PHY for TSMC 16nm Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 PH...

625 0.0

DDR5/4 Memory PHY for Samsung SF5A Automotive Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 PH...

626 0.0

DDR4/3 Memory PHY for TSMC N7 Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the Denali Hi...

627 0.0

DDR5/4 PHY for Samsung 7LPP Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 PH...

628 0.0

LPDDR4X/4/3/DDR4 PHY for TSMC 12nm and 16nm Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and exten...

629 0.0

DDR5/4/LPDDR5/4X PHY for TSMC for N5P Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and exten...

630 0.0

LPDDR5/5X Memory PHY for TSMC N3P Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly succe...

631 0.0

LPDDR5/5X Memory PHY for TSMC N5P Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly succe...

632 0.0

LPDDR5/5X Memory PHY for TSMC N4P Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly succe...

633 0.0

LPDDR5/4X PHY IP for TSMC N7 Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly succe...

634 0.0

GDDR6 PHY for TSMC N6 High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...

635 0.0

DDR4 PHY Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-mod...

636 0.0

DDR3 PHY Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-mod...

637 0.0

DDR4 Multi-modal PHY Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-mod...

638 0.0

GDDR6 Memory PHY for TSMC N5P Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...

639 0.0

GDDR6 Memory PHY for TSMC N7 Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...

640 0.0

GDDR7 Memory PHY for TSMC N3P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...

641 0.0

GDDR7 Memory PHY for TSMC N4P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...

642 0.0

GDDR7 Memory PHY for TSMC N5P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...

643 0.0

High Bandwidth Memory (HBM3E) 3 PHY for TSMC N3P Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is o...

644 0.0

High Bandwidth Memory (HBM3E) 3 PHY for TSMC N5P Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is o...

645 0.0

High Bandwidth Memory (HBM3E) 3 PHY for TSMC N7 Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3) PHY is op...

646 0.0

High Bandwidth Memory (HBM2E) HBM2E PHY for TSMC N7 Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-per...

647 0.0

High Bandwidth Memory (HBM2E) HBM2E PHY for Samsung 11nm Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor HBM2E is a high-per...

648 0.0

High Bandwidth Memory (HBM2E) HBM2E PHY for Global Foundries 12nm Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-per...

649 0.0

LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...

650 0.0

Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features The SPI-MEM-CTRL core from Alma Technologies offers the interconnection between a host and an SPI Flash memory device. The SPI-MEM-CTRL supports Singl...