51 100.0

PCIe 7.0 Controller with AXI The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...

52 100.0

PCIe 7.0 Switch The Rambus PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations. It enable...

53 100.0

CXL 2.0 Integrity and Data Encryption Security Module The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators...

54 90.0

Compute Express Link (CXL) 2.0 Controller Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache a...

55 90.0

Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambu...

56 85.0

PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...

57 85.0

PCIe 5.0 Controller with AMBA AXI interface Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...

58 80.0

PCIe 5.0 Customizable Embedded Multi-port Switch Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one u...

59 76.0

MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5 The MXL-CDPHY-DSI-TX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...

60 75.0

HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The HDMI Transmitter (TX) IP offerings adhere to HDMI 2.0 and 1.4 standards, offering the essential components for diverse design implementations. The...

61 75.0

MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1. The Arasan MIPI CSI-2 Transmitter IP Core functions as a MIPI Camera Serial Interface between a peripheral device (display module) and a host processo...

62 75.0

CXL 2.0 Agilex FPGA Acclerator Card Mobiveil’s CXL-Aglx Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applicatio...

63 70.0

PCIe Switch for USB4 Hubs, Hosts and Devices Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...

64 70.0

PCIe Controller Testbench PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...

65 70.0

PCIe 6.2 Switch The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the con...

66 70.0

CXL 3.0 IP EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled spee...

67 70.0

40G UCIe PHY IP on Samsung SF4X Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

68 65.0

MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...

69 65.0

MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7 The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...

70 60.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

71 60.0

MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and D...

72 60.0

DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

73 60.0

MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm The I3C bus (incl. PHY) is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and vario...

74 60.0

MIPI D-PHY IP 4.5Gbps in TSMC N7 The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

75 55.0

USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core Our company offers a highly configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications. This controller adhe...

76 51.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

77 50.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe ...

78 50.0

MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification. It supports both the MIPI Camera Serial Interface (CSI-2) an...

79 50.0

PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...

80 50.0

PCIe 4.0 Controller with AMBA AXI interface Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...

81 50.0

MIPI M-PHY - TSMC 40nm MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...

82 50.0

MIPI DSI-2 Receiver Controller v1.0 The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile display modules with T...

83 50.0

UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0 The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...

84 50.0

USB 2.0 nanoPHY in SMIC (65nm) The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...

85 50.0

40G UCIe PHY for organic substrate standard packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

86 50.0

40G UCIe PHY for high-density advanced packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

87 50.0

MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+ The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Display Serial Interface (...

88 50.0

USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0...

89 50.0

HDMI 2.1 Tx PHY in TSMC (16nm, 12nm, N7, N6, N4, N3E) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

90 50.0

HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

91 50.0

MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...

92 50.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

93 50.0

AHB Octal SPI Controller with Execute in Place The Octal Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and wr...

94 50.0

PCIe Gen3 to SRIO Gen3 Bridge (FPGA) Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...

95 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

96 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

97 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

98 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

99 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

100 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...