501 10.0

USB 3.0 PHY in Samsung (28nm, 14nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

502 10.0

USB 3.0 PHY in UMC (65nm, 40nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

503 10.0

USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, N7, N6) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

504 10.0

Multi-protocol, Low Power Serdes - TSMC 28 CLN28HPL Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

505 10.0

PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

506 10.0

Programmable Low Power V-by-One SERDES - GLOBALFOUNDRIES 65 65G Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

507 10.0

PCIe/HCSL Differential IO Buffer - TSMC 16FFC Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...

508 10.0

PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

509 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

510 10.0

Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

511 10.0

USB-C 3.1/DP TX PHY in Samsung (14nm, 11nm, 5nm) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

512 10.0

1-10G Low Power SERDES - TSMC 40G Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

513 10.0

Low Power PCIe3 SERDES PHY - TSMC 40G Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

514 10.0

Low Power PCIe3/SATA3SERDES PHY - TSMC 28HPC+ Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

515 10.0

Low Power PCIe3/SATA3 SERDES PHY - TSMC 16FFC Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

516 10.0

Low Power PCIe3/SATA3 SERDES PHY - TSMC 12FFC Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

517 10.0

High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

518 10.0

1-15G SERDES PCIe3/HMC SERDES PHY - TSMC 16FF+GL Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

519 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

520 10.0

PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

521 10.0

PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+ Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

522 10.0

USB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

523 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

524 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+ Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

525 10.0

PCIe3 SSCG PLL - TSMC 12FFC Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

526 10.0

PCIe3 SSCG PLL - TSMC 16FFC Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

527 10.0

PCIe4 Ethernet SERDES PHY - TSMC N5 Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

528 10.0

PCIe5 Ref Clock SSCG PLL - TSMC 6FF Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...

529 10.0

USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3A) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

530 10.0

12G Ethernet PHY in UMC (28nm) The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

531 10.0

16G PHY in Samsung (14nm, 11nm) The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

532 10.0

16G PHY in TSMC (28nm, 16nm, 12nm, N7, N6) The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

533 10.0

25G PHY in TSMC (16nm, 12nm, N7, N6) The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and ...

534 10.0

USB 3.1 Controller IP The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

535 10.0

USB 3.0 Digital Controller IP The Synopsys SuperSpeed USB IP solution is implemented in hundreds of designs and shipped in millions of units. The USB IP solution is based on the US...

536 10.0

USB 1.1 Digital Controller IP The Synopsys USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum. The Synopsys USB 1.1 IP offerin...

537 10.0

I2C & SMBus Controller The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The cor...

538 10.0

USB 2.0 Digital Controller IP The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on USB specification from...

539 10.0

USB 3.2 Controller IP The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...

540 10.0

Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

541 10.0

Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

542 10.0

Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

543 10.0

Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

544 10.0

Configurable CCIX controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications Synopsys’ complete CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 32GT/s and supports cache co...

545 10.0

IP Solutions for the AMBA Interconnect The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAs...

546 10.0

UFS Host Controller IP Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

547 10.0

32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2) The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and c...

548 10.0

Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane The CL12822M4R2JM2LIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12822M4...

549 10.0

Automotive MIPI A-PHY Sink IP (2-Lane) The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

550 10.0

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...