601 6.0

MIPI Rx D-PHY ...

602 6.0

USB 2.0 PHY; SMIC 55nm LL ...

603 6.0

AXI- Interconnect : Advanced Extensible Interface Bus IP The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-...

604 6.0

I2C Master/Slave Controller Core IP I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...

605 6.0

USB based High Speed System Debug IP Architecture Independent Design Supports any AMBA AHB based System Easily portable to other buses such as Avalon Standard USB 2.0 interface to th...

606 5.0

Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Slave Digital Controller is a fully integrated protocol manager intended to interface the UICC (SWP slave) to the NFC c...

607 5.0

Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Master Analog Front End (AFE) is a fully integrated interface intended to connect the NFC chip (SWP master) to the UICC...

608 5.0

Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Slave Analog Front End (AFE) is a fully integrated interface intended to connect the UICC (SWP slave) to the NFC chip (...

609 5.0

MIPI DSI-2 Transmitter Interface IP MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...

610 5.0

Interlaken Controller Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...

611 5.0

SATA PHY Gigacom's VSL340 PHY is suitable for both Host and Device applications within a Serial ATA system. The VSL340 PHY operates to the Serial ATA specifica...

612 5.0

SerialLite PHY with PCS The VSG1G55SL2 is an enhanced High-Speed SerialLite macro with data transfer capabilities of up-to 3.125Gbps. It includes the PCS layer within the Mac...

613 5.0

USB 2.0 Device Controller ...

614 5.0

USB 2.0 Host Controller ...

615 5.0

PCIe Gen3 PHY * Endpoint or Root Complex * PCIe standard multi-lane interface * PCIe power savings modes * Port bifurcation support...

616 5.0

Low/Full Speed USB Physical Layer CT25201 is a complete and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant device. ...

617 5.0

eUSB Repeater CT20603 IP implements a dual-role capable eUSB2 repeater enabling an eUSB2 PHY in SOCs to support connections with USB2.0 compliant hosts and peripher...

618 5.0

USB-C Interface CT20601 is a complete USB Type-C Interface which includes optional VCONN and VBUS management features. It implements the dual-role port CC1/CC2 inte...

619 5.0

SATA/SAS 3.0 PHY With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...

620 5.0

MIPI Compliant D-PHY TSMC 65LP Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

621 5.0

MIPI-I3C HOST (SDR) MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...

622 5.0

MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...

623 5.0

MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1 MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...

624 5.0

USB Power Delivery 3.1 Physical Layer CT20602 is a complete USB Power Delivery 3.1 Physical Layer. It also implements that part of the USB Power Delivery 3.1 Protocol Layer which are def...

625 5.0

SOF-Calibrated 48MHz USB Clock CT20101 extracts a precise 48MHz clock frequency underlying a USB 1.1 data stream. The device implements a loop that controls the output frequency o...

626 5.0

Low/Full Speed USB Billboard Controller The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device. It integrates all necessary infrastructures, including the CT201...

627 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

628 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

629 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

630 5.0

UART Serial Interface Controller The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...

631 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

632 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

633 5.0

Configurable Timer Counter The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...

634 5.0

Configurable System Tick Counter The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...

635 5.0

Configurable Watchdog Timer The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...

636 5.0

General Purpose Input/Output Controller The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

637 5.0

General Purpose Input/Output Controller The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

638 5.0

Advanced Encryption Standard Module The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...

639 5.0

USB3.2 Device Controller MosChip USB 3.2 Device Controller softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Device implementations along with...

640 5.0

SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus) The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...

641 5.0

MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP The MXL-CPHY-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master support...

642 5.0

MIPI SPMI Target Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

643 5.0

MIPI I3C Basic Target The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...

644 5.0

MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...

645 5.0

MIPI D-PHY Universal IP in Samsung 28FDSOI The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slav...

646 5.0

Power Management IC - I3C Basic Interface IP Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...

647 5.0

MIPI SPMI Host Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

648 5.0

USB3.2 Gen2x2 xHCI Host Controller MosChip USB3.x Host softcore is designed for embedded host applications with USB SSP operations and fall back support of SS and USB2 speed modes over ...

649 5.0

USB3.2 Retimer Controller MosChip USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations The IP has ...

650 5.0

USB 2.0 Hub Controller ...