901 1.0

RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...

902 1.0

Digital Down Converter core The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...

903 1.0

RSA public key cryptography with APB interface The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be...

904 1.0

MIPI C-PHY RX PHY The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...

905 1.0

MIPI C-PHY DSI RX IP Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...

906 1.0

MIPI C-PHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...

907 1.0

MIPI C/D-PHY RX The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...

908 1.0

MIPI C/D-PHY CSI-2 RX IP Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...

909 1.0

MIPI DSI-2 DSC RX IP Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...

910 1.0

MIPI CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

911 1.0

MIPI CSI-2 TX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

912 1.0

MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI) The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...

913 1.0

MIPI C-PHY TX PHY The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...

914 1.0

MIPI C/D-PHY TX The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...

915 1.0

MIPI D-PHY TX The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

916 1.0

MIPI D-PHY TX COMBO LVDS PHY The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...

917 1.0

MIPI D-PHY TX Combo TTL PHY The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

918 1.0

MIPI D-PHY_2.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

919 1.0

MIPI D-PHY_1.2G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

920 1.0

MIPI D-PHY_1.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

921 1.0

MIPI D-PHY_4.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

922 1.0

MIPI D-PHY CSI-2 RX IP Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...

923 1.0

MIPI D-PHY Combo LVDS CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...

924 1.0

MIPI DPHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

925 1.0

MIPI D-PHY DSI 1.2G RX IP Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...

926 1.0

MIPI D-PHY DSI 1.5G RX IP Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...

927 1.0

MIPI D-PHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

928 1.0

MIPI D-PHY Combo LVDS DSI TX IP Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...

929 1.0

MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI) The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...

930 1.0

MIPI M-PHY TX/RX + Controller INNOSILICON M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of group of communication protocols defined by MIPI ...

931 1.0

64G/56G SerDes The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...

932 1.0

JESD204B Controller JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...

933 1.0

JESD204B PHY & Controller JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...

934 1.0

5G Multi-SerDes For PCIe2.0/USB3.0 PHY The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the P...

935 1.0

8G Multi-SerDes For PCIe3.0/USB3.0 PHY The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the P...

936 1.0

PCIe2.0 PHY & Controller The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet,...

937 1.0

PCIe2.1 PHY The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet,...

938 1.0

PCIe3.0 Controller The Innosilicon Gen1/2/3 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, high ...

939 1.0

PCIe3.0 PHY The Innosilicon PCIe3.0 PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this particular datasheet,...

940 1.0

PCIe4.0 Controller The Innosilicon Gen1/2/3/4 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, hig...

941 1.0

PCIe4.0 PHY The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...

942 1.0

PCIe5.0 PHY & Controller The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...

943 1.0

SGMII PHY The Innosilicon SGMII PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 1000BAS...

944 1.0

PCIe4/3/2/1 PHY & Controller The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...

945 1.0

Type-C PHY Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...

946 1.0

USB3.1/3.0 PHY & Controller The Innosilicon USB3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface fo...

947 1.0

USB 3.0 DRD Controller Innosilicon USB3.0 DRD Controller provides a USB3.0-compliant host/device controller solution. This controller can be programmed to support data trans...

948 1.0

USB2.0 OTG PHY The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent perf...

949 1.0

USB2.0 PHY & Controller The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent perf...

950 1.0

USB 2.0 DRD Controller Innosilicon USB2.0 DRD Controller provides a USB2.0-compliant host/device controller solution. This controller can be programmed to support data trans...