1201 0.118

USB 2.0 OTG PHY IP, UMC 90nm SP process USB2.0 OTG PHY, UMC 90nm SP/RVT/ Low-K process....

1202 0.118

USB 2.0 OTG PHY IP, UMC 90nm LL process USB2.0 OTG PHY, UMC 90nm LL Low-K -RVT process 2.5V OD 3.3V....

1203 0.118

USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process USB3.0 PHY, UMC 0.11um HS/AE Logic process....

1204 0.118

USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process....

1205 0.118

USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process....

1206 0.118

USB 3.0 OTG PHY IP, UMC 55nm SP process USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process....

1207 0.118

USB 3.0 OTG PHY IP, UMC 90nm SP process USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process....

1208 0.0

32-bit, 33 MHz PCI Target Interface Core The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the u...

1209 0.0

1.5G MIPI D-PHY in SMIC 130nm~28nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

1210 0.0

2.5G MIPI D-PHY in HLMC 28nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

1211 0.0

2.5G MIPI D-PHY in TSMC 22nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

1212 0.0

6.25G SerDes in 55nm The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels. It’s based on SMIC 55nm embedded-flash tec...

1213 0.0

16G SerDes in 28nm The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data communication while operat...

1214 0.0

SATA Port Multiplier with Sandbox The IntelliProp IPP-SA128A-PM (SATA Port Multiplier with Sandbox) device is an IP core that provides SATA Port Multiplier functionality with support f...

1215 0.0

128 Channel Analog Front-End PMCC_XCM_64X64_A IP block is a 128 channels analog front-end. The IP block consists of 128 variable gain amplifiers (VGAs), 128 2-bit digitizers, bias...

1216 0.0

Digital FIR filter with APB interface The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....

1217 0.0

APB Subsystem The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...

1218 0.0

SPI to AMBA AHB Master Bridge The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...

1219 0.0

AMBA AHB Slave to Local Interface Bridge The Veriest AMBA AHB Slave Bridge Design IP offers a simple solution to provide a bridge between the embedded AMBA AHB bus and a simplified generic lo...

1220 0.0

AMBA AHB Simple Master Bridge The Veriest AMBA AHB Simple Master Bridge Design IP provides a bridge between the embedded AMBA AHB bus master and a simplified generic local bus. The...

1221 0.0

Register Indirect RAM Access The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devi...

1222 0.0

AMBA AXI Performance Monitor The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility ...

1223 0.0

AMBA AHB Address Trapper The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order...

1224 0.0

AMBA AXI Data Writer Spreader The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data ma...

1225 0.0

AMBA AXI Data Prefetch Buffer The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM...

1226 0.0

HDMI ver1.3 Receiver IP HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product (HD-TV, AV receiver....

1227 0.0

HDMI ver1.3 Transmitter IP HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' product (HD-TV, AV receive...

1228 0.0

HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55LP HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification. This HDMI RX PHY supports from 25MHz...

1229 0.0

HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55GP Physical layer IP core for HDMI transmitters that complies exactly with HDMI 1.4 specifications The HDMI transmitter PHY provides a straight forward i...

1230 0.0

HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz ...

1231 0.0

HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification. The HDMI TX PHY supports from 25MHz to 250MHz pixe...

1232 0.0

HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55GP A single-port IP core called the HDMI receiver PHY (Physical layer) is completely compliant with HDMI 1.4's specifications. This HDMI RX PHY provides ...

1233 0.0

HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55LP HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification. HDMI transmitter PHY supports from 25MHz to 250MHz...

1234 0.0

MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and ...

1235 0.0

MIPI UFS v2.1 Host Controller IP, Compatible with M-PHY and Unipro UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and ...

1236 0.0

MIPI Unipro v1.8 Controller IP, Compatible with M-PHY and UFS This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a ...

1237 0.0

USB 3.0 High/Full/Low-Speed Host + Device Controller IP USB 3.0 Dual Mode Controller IP Core uses a high performance DMA engine based on the xHCI specification and presenting either an AHB or AXI interface,...

1238 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Low pow...

1239 0.0

USB 3.0 Gen1 / Gen2 Device Controller IP We provide highly configurable and scalable USB 3.0 host/device/dual mode controller IP Core for a wide range of applications. The USB 3.0 controller ...

1240 0.0

USB 3.1 Gen1 / Gen2 Device Controller IP USB 3.1 Device controller is a highly configurable core and implements the USB 3.1 Device functionality that can be interfaced with third party USB 3....

1241 0.0

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) ...

1242 0.0

MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core. It is compatible with the Display Serial Inter...

1243 0.0

USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USB?IF) and is compatible with the latest xHCI 1.1 ...

1244 0.0

MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+ The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, Uni...

1245 0.0

HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+ The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver. In DisPlay Port mode, the receiver is...

1246 0.0

ISO 7816 based Smart Card Reader IP The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...

1247 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+ The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) com...

1248 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

1249 0.0

Tiny UART The DUART is one of the tiniest UART IP Cores available on the market. The DUART is a soft core of a Universal Asynchronous Receiver/Transmitter (U...

1250 0.0

USB 1.1 Device Controller IP USB 1.1 Device Controller IP is based on the latest USB 1.1 specification from USB Implementer Forum (USB-IF) and is compatible with the latest xHCI 1...