1351 0.0

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+ The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface sp...

1352 0.0

USB 3.1 Gen1 / Gen2 Host Controller IP USB 3.1 Host Controller is compliance with USB3.1 specification, Revision 1.0 and all associated ECN’s, USB specifications Rev 2.0 and all associated ...

1353 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interface protocols (USB Hig...

1354 0.0

AXI Subsystem The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...

1355 0.0

AXI Interface Core Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and read ...

1356 0.0

PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...

1357 0.0

PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...

1358 0.0

PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 ...

1359 0.0

SATA 3.0 Host Controller The Chevin Technology SATA-HC IP block simplifies the integration of high capacity SSDs utilizing SATA I/II/III at 1.5/3/6Gbit/s data rates using Xili...

1360 0.0

AHB Multilayer Interconnect The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...

1361 0.0

VDC-M 1.2 Decoder The BTREE VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression). Its visually lossless compression performance is up to 5...

1362 0.0

VDC-M 1.2 Encoder The BTREE VDC-M 1.2 Encoder IP Core fully complies with VESA VDC-M 1.2(Display Compression). Its visually lossless compression performance is up to 5:...

1363 0.0

ONFI 2.3 NAND Flash Controller The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...

1364 0.0

PCIE Gen6 digital controller (End Point) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1365 0.0

CXL 3.0 Dual Mode Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1366 0.0

MIPI D-PHY TSMC 28nm HPM The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...

1367 0.0

Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.2 @ 2.5GHz Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 22nm FinFET process nodes. Arasan's D-PHY Global Foun...

1368 0.0

MIPI D-PHY in ON Semiconductor 180nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

1369 0.0

I/O LIbrary Specialty I/O solutions - Higher voltage tolerance - higher ESD robustness - Configurable...

1370 0.0

MIPI D-PHY TSMC 40LP Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

1371 0.0

Chiplet Solution Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...

1372 0.0

eDisplayPort v1.4 Receiver Controller IP Core This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...

1373 0.0

PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specification...

1374 0.0

Low Power Dual PHY for UCIe low cost robust Chiplets YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...

1375 0.0

PCIe 6.0 PHY for TSMC N3P The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

1376 0.0

AXI Multilayer Interconnect The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...

1377 0.0

MIPI M-PHY Designed For TSMC 28nm ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...

1378 0.0

USB 3.0 Device Upgrade IP Core The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhan...

1379 0.0

AXI to APB Bridge The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...

1380 0.0

USB 2.0 PHY TSMC 40G The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

1381 0.0

USB 2.0 PHY IBM 180 The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

1382 0.0

MIPI D-PHY in GlobalFoundries 40nm Automotive Process Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

1383 0.0

MIPI D-PHY UMC 40LL Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

1384 0.0

MIPI Soundwire PHY The physical layer block implements all the line-side functions such as NRZI encoding & decoding, bus clash detection, data line buffer enable/disable...

1385 0.0

MIPI D-PHY V1.2@2.5GHz Tx only Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...

1386 0.0

Globalfoundries 12nm MIPI D-PHY Tx only V1.2@2.5GHz Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...

1387 0.0

Globalfoundries 12nm MIPI D-PHY Rx only V1.2@2.5GHz Arasan Chip Systems standalone MIPI D-PHY(SM) Recieve (Rx) only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Rx only for...

1388 0.0

VESA DSC V1.2 Encoder The Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8,...

1389 0.0

MIPI DSI-2 with VESA DSC Arasan’s Total IP Solution for MIPI Display Serial Interface (DSI-2) with VESA DSC IP provides both device and host functionality along with VESA DSC ...

1390 0.0

MIPI DSI-2 Transmit Controller v2.0 Arasan’s Display Host and DSI device controllers are built on existing MIPI Alliance standards by adopting pixel formats, controlling pins and comma...

1391 0.0

MIPI SPMI 2.0 Device IP Arasan’s SPMI Device IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols. It is designed to be configured as a SPMI Host, SPMI Device...

1392 0.0

GLink Multi-Slice PCS GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...

1393 0.0

GLink AXI Wrapper GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...

1394 0.0

GLink CXS-Bridge GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...

1395 0.0

GLink Multi-Slice PCS GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...

1396 0.0

TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4,SAS-3 G1-G4, SATA-...

1397 0.0

TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G...

1398 0.0

TSMC CLN5FF GLink 2.3LL Die-to-Die PHY IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...

1399 0.0

TSMC CLN5FF GLink GPIO IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...

1400 0.0

TSMC CLN5FF GLink 2.0 Die-to-Die PHY IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...