1601 0.0

AMBA AHB to APB Bus Bridge Core The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...

1602 0.0

General-Purpose I/O Controller Core The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...

1603 0.0

Internal Synchronous SRAM Controller Core The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...

1604 0.0

Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...

1605 0.0

MIPI D-PHY 4 Lane CSI-2 TX (Transmitter) in TowerJazz 110nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

1606 0.0

Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane * The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data strea...

1607 0.0

RGB to CCIR 601 / 656 Encoder The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...

1608 0.0

BitBLT Graphics Hardware Accelerator (AXI4 Bus) The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

1609 0.0

I2C Master Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

1610 0.0

I2C Master Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...

1611 0.0

eSPI & SPI Master Controller w/FIFO The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

1612 0.0

eSPI & SPI Slave Controller w/FIFO The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

1613 0.0

I2C Bus Interface - Master The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices...

1614 0.0

Slave I2C bus controller with FIFO The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as: - a slave transmitter or - slave receiv...

1615 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY...

1616 0.0

I2C Bus Interface Slave -Base version The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...

1617 0.0

I2C Bus Interface - Master/Slave The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...

1618 0.0

USB 2.0 Device Controller The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The DUSB2 contains the USB ...

1619 0.0

Digital IIR filter with APB interface A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...

1620 0.0

APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....

1621 0.0

MIPI D-PHY 2-Lane CSI-2 TX (Transmitter) in TowerJazz 65nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. Th...

1622 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 22ULL The MXL-DPHY-CSI-2-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1623 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 55ULP The MXL-DPHY-DSI-TX-T-55ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...

1624 0.0

PCI to AMBA AHB Host Bridge This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...

1625 0.0

AHB Low Power Subsystem - ARM M0 The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...

1626 0.0

AHB Performance Subsystem - ARM M3 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...

1627 0.0

FPGA Proven PCIe GEN6 Controller PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...

1628 0.0

PCIe GEN6 PHY Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...

1629 0.0

CXL 3 Controller The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for...

1630 0.0

USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm) USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...

1631 0.0

AXI Performance Subsystem The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. ...

1632 0.0

MIPI D-PHY Universal IP The MXL-PHY-MIPI is a high-frequency low-power, low cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Alth...

1633 0.0

MIPI PLL The MXL-PLL-MIPI-PXL is a high performance PLL based frequency synthesizer implemented using digital CMOS technology. It is highly integrated and requ...

1634 0.0

MIPI D-PHY CSI-2 RX (Receiver) IP The MXL-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1635 0.0

MIPI M-PHY Compliant (HS-G2) IP The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

1636 0.0

MIPI M-PHY DigRF Compliant IP The MXL-M-PHY-DIGRF is a high frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY and DigRF. The IP c...

1637 0.0

MIPI D-PHY DSI TX (Transmitter) IP The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1638 0.0

MIPI D-PHY DSI RX (Receiver) IP The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1639 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY....

1640 0.0

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC The MXL-CD-PHY-DSIRX+-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1641 0.0

MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL The MXL-CPHY-2p5G-DSI-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

1642 0.0

AXI Interconnect Fabric The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...

1643 0.0

CXL 3.0 Host Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1644 0.0

PCIE Gen6 digital controller (Root Complex) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1645 0.0

PCIE Gen6 digital controller (Dual Mode) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1646 0.0

CXL 3.0 Device Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1647 0.0

PCIe Gen6.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1648 0.0

CXL 3.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1649 0.0

AXI to AHB Lite Bus Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1650 0.0

CXL 2.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...