301 20.0

HDMI 2.1 Tx PHY in GF (12nm) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

302 20.0

HDMI 2.1 Tx PHY in Samsung (14nm) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

303 20.0

PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm) The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...

304 20.0

PCIe 3.0 PHY in GF (28nm, 22nm) The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

305 20.0

Synopsys PCIe 4.0 PHY IP for TSMC N7 The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

306 20.0

PCIe 4.0 PHY in GF (14nm, 12nm) The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

307 20.0

MIPI DSI-2 host/device controllers for high-speed serial interface between application processor and displays Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

308 20.0

USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

309 20.0

PCIe 2.0 PHY in Fujitsu (40nm) The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...

310 20.0

PCIe 2.0 PHY in SMIC (40nm, 28nm) The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...

311 20.0

PCIe 2.0 PHY in TSMC (28nm, 16nm, 12nm) The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...

312 20.0

PCIe 2.0 PHY in UMC (40nm, 28nm) The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...

313 20.0

PCIe 3.0 PHY in UMC (28nm) The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

314 20.0

PCIe 4.0 PHY in Samsung (14nm, 11nm, SF5A, SF2) The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

315 20.0

IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a ...

316 20.0

MIPI CSI-2 host/device controllers for high-speed serial interface between image processor and camera sensors Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

317 20.0

MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

318 20.0

MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

319 20.0

MIPI UniPro IP for reliable, high-performance and low power link between devices in mobile devices Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

320 20.0

Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex inter...

321 20.0

MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm and 40nm) MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...

322 18.0

Die-2-die interfaces for chiplets Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...

323 18.0

Analog I/O - low capacitance, low leakage Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven) Ultra-low leakage Low para...

324 18.0

on-chip ESD protection Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...

325 18.0

1.8V general purpose I/O for 4nm FinFET The Sofics 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. I...

326 17.0

28Gbps MR SerDes IP on TSMC 28nm Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates. This SerDes PMA is silicon proven...

327 17.0

28Gbps LR SerDes IP on TSMC 28nm Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rate. Features include excellent insertio...

328 17.0

56Gbps LR SerDes IP on TSMC 16/12nm Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates. Features include the lowest power i...

329 17.0

56Gbps LR SerDes IP on TSMC 7nm Credo is the world leading SerDes Technology. SerDes PMA is silicon proven IP offers in TSMC 7nm processes. Features include excellent insertion loss...

330 17.0

AXI2APB Bridge Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....

331 16.0

AHB-Lite APB4 Bridge The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...

332 16.0

AHB-Lite Multilayer Switch The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...

333 16.0

APB4 Multiplexer The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...

334 16.0

AHB-Lite General Purpose Memory Module The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...

335 16.0

APB4 General Purpose Input/Output Module The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...

336 16.0

AHB-Lite Timer The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...

337 16.0

RISC-V Compliant Platform Level Interrupt Controller Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...

338 16.0

3.3V general purpose I/O for 28nm CMOS The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It ...

339 16.0

USB2.0 Host Transceiver PHY USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...

340 15.0

Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2 The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...

341 15.0

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...

342 15.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...

343 15.0

PCIe 5.0 PHY With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...

344 15.0

MIPI D-PHY Universal IP in TSMC 40LP for Automotive The MXL-DPHY-UNIVERSAL-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard fo...

345 15.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 16FFC he MXL-DPHY-CSI-2-RX-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification f...

346 15.0

MIPI D-PHY CSI-2 RX+ (Receiver) IP in UMC 40ULP The MXL-DPHY-CSI-2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PH...

347 15.0

Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane * The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...

348 15.0

High Performance Second Generation Extended MIPI CSI2 Receiver Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwee...

349 15.0

Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwee...

350 15.0

DP/eDP1.4b RX Controller Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....