51 2.0

1.8V General Purpose I/O Staggered Pad Set The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system d...

52 2.0

1.8V General Purpose I/O Staggered Pad Set The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system d...

53 2.0

LVDS IO Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...

54 2.0

3.3V Fault Tolerant General Purpose I/O Staggered Pad Set The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant. These programmable, multi-voltage I/O’s give the sy...

55 2.0

3.3V Fault Tolerant General Purpose I/O Inline Pad Set The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant. These programmable, multi-voltage I/O’s give the sy...

56 2.0

3.3V General Purpose I/O Staggered Pad Set The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibili...

57 2.0

3.3V General Purpose I/O Inline Pad Set The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibili...

58 2.0

1.8V General Purpose I/O Staggered Pad Set The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

59 2.0

3.3V Wide-Range General Purpose Inline I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

60 2.0

1.8V General Purpose Staggered I/O Pad Set The 1.8V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibili...

61 3.0

Voltage Domain Interfacing Cells for use between power domains using core transistors. Level Shifter with CDM protection are Domain Interfacing Cells. Provided as High-Low and Low-High level shifters including isolation and CDM protectio...

62 0.0

3.3V Wide-Range General Purpose Inline I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...

63 0.0

SSTL_15_18 IO Pad Set The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...

64 0.0

subLVDS IO Pad Set The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 14...

65 0.0

LVDS IO Pad Set The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit...

66 0.0

2.5V 5V Tolerant GPIO Staggered IO Pad Set The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...

67 0.0

2.5V 5V Tolerant GPIO Inline IO Pad Set The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...

68 0.0

ONFI IO Pad Set The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support bo...

69 0.0

2.5V General Purpose Staggered IO Pad Set A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...

70 0.0

2.5V General Purpose Inline IO Pad Set A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...

71 20.0

LPDDR5X/5/4X/4 combo PHY at 7nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

72 0.0

6 track Ultra High Density standard cell library at TSMC 180 nm TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...

73 5.0

EverOn Ultra Low Voltage Embedded SRAM TSMC 40ULP sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...

74 5.0

EverOn Ultra Low Voltage Embedded SRAM TSMC 28HPC+ sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...

75 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 28HPC+ PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

76 5.0

EverOn Ultra Low Voltage Embedded SRAM TSMC 40ULP Embedded Flash sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...

77 8.0

SureFIT Custom SRAM Design Service Provides a SRAM design service customised to customer specification. SureFIT deploys silicon proven and patented low-power design techniques with powe...

78 5.0

EverOn Ultra Low Voltage Embedded SRAM TSMC 22ULL sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...

79 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 22ULL PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

80 7.0

PowerMiser Ultra Low Power Embedded SRAM SE 28FDS PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

81 4.0

Cryogenic SP SRAM qualified down to 4K operating temperature Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...

82 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

83 0.0

7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V) TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...

84 0.0

In-memory computing CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data ...

85 0.0

Four Channel LVDS Serializer in TSMC 130nm The MXL-SR-LVDS-4CH7-130 is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data ...

86 20.0

MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI ...

87 0.0

Four Channel (4CH) LVDS Serializer in Samsung 28FDSOI The 28FDSOI-LVDS-4CH-TX-1250-PLL is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parall...

88 0.0

Eight Channel (8CH) LVDS Serializer in Samsung 28FDSOI The 28FDSOI-LVDS-1250-8CH-TX-PLL is a high performance 8-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parall...

89 12.0

180nm MTP Non Volatile Memory for Standard CMOS Logic Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

90 12.0

FTP Non Volatile Memory for Standard TSMC 40nm ULP Process NSCore's TwinBit(TM)FTP is the only embedded CMOS, few-time programmable (FTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to...

91 12.0

MTP Non Volatile Memory for TSMC 180nm BCD Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

92 12.0

55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

93 10.0

Single Port SRAM Compiler GlobalFoundries 55LPx Ultra-high density, low power, up to 320K bits Proven Single Port SRAM compiler for GF55 LPx - Memory optimized for ultra high density and high speed with compiler range up to 320K bits...

94 0.0

9 track Near Threshold Voltage standard cell library at TSMC 55 nm TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...

95 10.0

ONFI 3.0 Compatible I/O Buffer - TSMC 28 CLN28HPM Analog Bits ONFI 3.0 compatible I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today’s ...

96 10.0

Differential Receiver - TSMC 7FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

97 10.0

Differential Output Buffer - TSMC 6FF Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

98 10.0

Differential Output Buffer - TSMC N5 Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

99 10.0

Differential Signal Receiver - TSMC 6FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

100 10.0

Differential Signal Receiver - TSMC N5 Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...