851 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library....

852 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40)....

853 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library....

854 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

855 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

856 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

857 0.3729

Low Power/Ultra Low Power Single Port Multi-banks SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...

858 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library....

859 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

860 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

861 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

862 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

863 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process UMC 55nm SP/HVT Low-K process POWERSLASH Cell Library....

864 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library....

865 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library....

866 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells....

867 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit....

868 0.3729

Low Power/Ultra Low Power One Port Register File (1 Port RF) Compiler with Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...

869 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library....

870 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

871 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process UMC 65nm SP/HVT process POWERSLASH Cell Library....

872 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version)....

873 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library....

874 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process UMC 90nm SP/RVT Low-K process Low Power standard Cell Library....

875 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary....

876 0.118

Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process UMC 0.18um GII Logic process True 1.8V Metal-programmable IO (MPIO) Cell Library....

877 0.118

Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler....

878 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process UMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option....

879 0.3729

Low Power/Ultra Low Power 2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...

880 0.118

Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process UMC 0.11um eFlash HS process, Dual Port SRAM compiler....

881 0.118

Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process UMC 0.11um eFlash LL process Dual Port SRAM compiler....

882 0.118

Dual Port SRAM Compiler IP, UMC 0.11um LL process UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler....

883 0.118

Dual Port SRAM Compiler IP, UMC 0.11um SP process UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler....

884 0.118

Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux....

885 0.118

Dual Port SRAM Compiler IP, UMC 0.13um LL process UMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler....

886 0.118

Dual Port SRAM Compiler IP, UMC 0.18um G2 process UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....

887 0.118

Dual Port SRAM Compiler IP, UMC 0.18um G2 process UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....

888 0.118

Dual Port SRAM Compiler IP, UMC 28nm HLP process UMC 28nm HLP/ Low-K Dual Port SRAM compiler....

889 0.118

Dual Port SRAM Compiler IP, UMC 28nm HLP process UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT....

890 2.0

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k Foundry Sponsored - Single Port SRAM compiler - TSMC 85 nm UP - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range...

891 0.3729

Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF Specialty Memory Solutions...

892 0.118

Dual Port SRAM Compiler IP, UMC 28nm HLP process UMC 28nm HLP Logic process, Dual Port SRAM compiler with R1....

893 0.118

Dual Port SRAM Compiler IP, UMC 55nm eHV process UMC 55nm eHV process, Dual Port SRAM compiler....

894 0.118

Dual Port SRAM Compiler IP, UMC 55nm LP process UMC 55nm LP/ Low-K process with row Redundancy Dual Port SRAM compiler....

895 0.118

Dual Port SRAM Compiler IP, UMC 90nm SP process UMC 90nm SP/RVT/ Low-K process synchronous Dual Port SRAM compiler....

896 0.118

General Purpose IO IP, SD3.0 I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC EMMC IO Cell Library (with customized PU/PD function)....

897 0.118

General Purpose IO IP, 5V tolerance, UMC 0.13um process UMC 0.13um 5V tolerance gengric IO....

898 0.118

General Purpose IO IP, UMC 0.13um process UMC 0.13um ture 3.3V Generic IO IP....

899 0.118

General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process UMC 0.18um GII Logic process 5V tolerance standard IO Cell Library....

900 0.118

General Purpose IO IP, UMC 0.18um G2 process UMC 0.18um GII Logic process true 1.8V standard IO Cell Library....