1051 0.118

Standard Cell (Generic) Library IP, UMC 0.18um LL process UMC 0.18um LL Logic process standard Core Cell Library....

1052 0.118

Standard Cell (Generic) Library IP, UMC 0.18um LL process UMC 0.18um LL Logic process mask programmable cell array with body E Core Cell Library....

1053 0.118

Standard Cell (Generic) Library IP, UMC 0.18um MS process UMC 0.18um Mixed-Mode / RFCMOS process standard Core Cell Library....

1054 0.118

Standard Cell (Generic) Library IP, UMC 0.25um process UMC 0.25um Logic process shrink (0.22um) mask programmable cell array with body A Core Cell Library....

1055 0.118

Standard Cell (Generic) Library IP, UMC 0.25um process UMC 0.25um Logic process mask programmable cell array with body E Core Cell Library....

1056 0.118

Standard Cell (Generic) Library IP, UMC 0.25um process UMC 0.25um Logic process standard Cell Library....

1057 0.3729

2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process GC Memory Compilers...

1058 0.118

Standard Cell (Generic) Library IP, UMC 0.25um process UMC 0.25um Logic process standard Cell Library....

1059 0.118

Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process UMC 90nm SP Logic Low-K process standard Core Cell Library....

1060 0.118

Standard Cell (MiniLib) Library IP, 7 tracks, HJTC 0.18um eFlash/G2 process HJTC 0.18um eFlash process Mini-Library....

1061 0.118

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process high density Core Cell Library....

1062 0.118

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/HVT Low-K Logic process 12-Track Standard Cell Library....

1063 0.118

Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/LVT Low-K Logic process 12-Track high performance Cell Library....

1064 0.118

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic process 12-Track high performance Cell Library....

1065 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38)....

1066 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Kit Cell Library C35....

1067 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library....

1068 0.3729

Metal Programmable ROM Compiler with Row/Column Redundancy Option, supports process GC Specialty Memory Solutions...

1069 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30)....

1070 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38)....

1071 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

1072 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35)....

1073 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT)....

1074 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38)....

1075 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

1076 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

1077 0.118

Two Port Register File Compiler IP, UMC 0.11um eFlash/HS process UMC 0.11um eFlash HS process, Two Port Register File....

1078 0.118

Two Port Register File Compiler IP, UMC 0.11um HS/AE process UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process synchronous Two Port Register File memory compiler....

1079 0.3729

High Performance/Low Power Ternary-CAM/Binary-CAM, supports process G/GT/LP/LPEF Specialty Memory Solutions...

1080 0.118

Two Port Register File Compiler IP, UMC 0.11um HS/FSG process UMC 0.11um HS Logic process synchronous Two Port Register File SRAM memory compiler....

1081 0.118

Two Port Register File Compiler IP, UMC 0.11um LL/FSG process UMC 0.11um Logic(LL) FSG process synchronous Two Port Register File memory compiler....

1082 0.118

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process UMC 0.13um HS/LL fusion (FSG) process high density synchronous Two Port Register File SRAM memory compiler....

1083 0.118

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler....

1084 0.118

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process UMC 0.13um Logic HS FSG Synchronous high density Low Power Two Port Register File SRAM memory compiler....

1085 0.118

Two Port Register File Compiler IP, UMC 0.13um LL process UMC 0.13um LL Logic/FSG process high density synchronous Two Port Register File SRAM memory compiler....

1086 0.118

Two Port Register File Compiler IP, UMC 0.18um G2 process UMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....

1087 0.118

Two Port Register File Compiler IP, UMC 0.25um process UMC 0.25um Logic process synchronous Two Port Register File compiler....

1088 0.118

Two Port Register File Compiler IP, UMC 0.25um process UMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....

1089 0.118

Two Port Register File Compiler IP, UMC 28nm HLP process UMC 28nm HLP/ Low-K Two Port Register File compiler....

1090 0.3729

High Performance/Low Power Dual Port SRAM Compiler with Row/Column Redundancy Option, supports process G/GT/LP/LPEF Memory Compilers...

1091 0.118

Two Port Register File Compiler IP, UMC 28nm HLP process UMC 28nm HLP peripheral LVT Two Port Register File memory compiler....

1092 0.0

Two Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....

1093 0.118

Two Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP/LVT process, Two Port Register File with LVT....

1094 0.118

Two Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....

1095 0.118

Two Port Register File Compiler IP, UMC 55nm LP process UMC 55nm LP/ Low-K process PG Two Port Register File compiler....

1096 0.118

Two Port Register File Compiler IP, UMC 90nm SP process UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler....

1097 0.118

One Port Register File Compiler IP, UMC 28nm HPC process UMC 28nm HPC process One Port Register File...

1098 0.118

ROM Compiler IP, UMC 28nm HPC process UMC 28nm HPC process Via ROM compiler...

1099 0.118

LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process LVDS RX, UMC 40nm LP/RVT Low-K Logic process....

1100 0.118

Standard Cell (RTC) Library IP, UMC 55nm ULP process UMC 55nm ULP/uHVT LowK Logic Process 2.5 V OD 3.3 V device RTC Core Library...