1151 0.118

Specialty PCI IO IP, UMC 0.45um Logic process UMC 0.45um Logic process Gate Array true 5.0V PCI IO cells....

1152 0.118

General Purpose IO IP, 5V tolerance, UMC 0.45um Logic process UMC 0.45um Logic process 5V tolerance low voltage gate array IO Cell Library....

1153 0.118

Specialty PCI IO IP, 5V tolerance, UMC 0.45um Logic process UMC 0.45um Logic process Gate Array Low Voltage 5.0V tolerant PCI IO cells....

1154 0.118

General Purpose IO IP, UMC 0.45um Logic process UMC 0.45um Logic process true 3.3V low voltage gate array IO Cell Library....

1155 0.118

Specialty PCI IO IP, UMC 0.45um Logic process UMC 0.5um Logic process Low Voltage Gate Array true 3.3V Oscillator IO cells....

1156 0.118

Specialty PCI IO IP, UMC 0.45um Logic process UMC 0.45um Logic process Gate Array Low Voltage true 3.3V PCI IO cells....

1157 0.3729

High Performance/Low Power Metal Programmable ROM Compiler with Row/Column Redundancy Option, supports process G/GT/LP/LPEF Specialty Memory Solutions...

1158 0.118

General Purpose IO IP, UMC 0.45um Logic process UMC 0.45um Logic process true 5V low voltage gate array IO Cell Library....

1159 0.118

Specialty PCI IO IP, UMC 0.45um Logic process UMC 0.45um Logic process Gate Array Low Voltage true 5.0V PCI IO cells....

1160 0.118

Standard Cell (Generic) Library IP, UMC 0.5um process UMC 0.5um Logic process standard Core Cell Library....

1161 0.118

Standard Cell (Generic) Library IP, UMC 0.5um process UMC 0.5um Logic process low voltage Core Cell Library....

1162 0.118

General Purpose IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 3.3V standard IO Cell Library....

1163 0.118

Specialty PCI IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 3.3V PCI IO cells....

1164 0.118

General Purpose IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 5V standard IO Cell Library....

1165 0.118

Specialty PCI IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 5.0V Oscillator IO cells....

1166 0.118

Specialty PCI IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 5.0V PCI IO cells....

1167 0.118

General Purpose IO IP, 5V tolerance, UMC 0.5um Logic process UMC 0.5um Logic process 5V tolerance low voltage IO Cell Library....

1168 0.3729

Ternary-CAM/Binary-CAM, supports process G/LV Specialty Memory Solutions...

1169 0.118

General Purpose IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 3.3V low voltage IO Cell Library....

1170 0.118

Specialty PCI IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 3.3V Oscillator IO cells....

1171 0.118

General Purpose IO IP, UMC 0.5um Logic process UMC 0.5um Logic process true 5V low voltage IO Cell Library....

1172 0.118

10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process 10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process...

1173 0.118

Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process...

1174 0.118

LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process...

1175 0.118

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad. LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad....

1176 0.118

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process...

1177 0.118

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process...

1178 0.118

3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process 3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process...

1179 0.3729

Dual Port SRAM Compiler with Row/Column Redundancy Option, supports process G/LV Memory Compilers...

1180 0.118

UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...

1181 0.118

UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...

1182 0.118

Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

1183 0.118

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

1184 0.118

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

1185 0.118

3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process 3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process...

1186 0.118

8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process 8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process...

1187 0.118

3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process 3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process...

1188 0.118

LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process...

1189 0.118

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip...

1190 0.3729

Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, supports process G/LV Memory Compilers...

1191 0.118

The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process...

1192 0.118

The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process...

1193 0.118

The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process...

1194 0.118

The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process...

1195 0.118

2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process 2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process...

1196 0.118

3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process...

1197 0.118

3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces...

1198 0.118

0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process 0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

1199 0.118

2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout ) 2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )...

1200 0.118

LVDS Transmitter 700Mbps; UMC 28nm HPC Process LVDS Transmitter 700Mbps; UMC 28nm HPC Process...