1601 2.0

3.3V Wide Ranging GPIO The 3.3V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog pow...

1602 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)...

1603 0.118

UMC 28nm HPM/HVT Logic Process 12-track powerslash_core library (C35) UMC 28nm HPM/HVT Logic Process 12-track powerslash_core library (C35)...

1604 0.118

UMC 28nm HPM/LVT Logic Process 12-track powerslash_core library UMC 28nm HPM/LVT Logic Process 12-track powerslash_core library...

1605 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library...

1606 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...

1607 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...

1608 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

1609 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1610 0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell. UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....

1611 0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell. UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....

1612 0.0

Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range up to 80 k...

1613 2.0

PCI IO Pad Set The PCI 3.0 library provides the driver / receiver and required support cells for PCI 3.0 signaling. The cells are compliant with the PCI Local Bus S...

1614 0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1615 0.118

UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library...

1616 0.118

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library...

1617 0.118

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library...

1618 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1619 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1620 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1621 0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1622 0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1623 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1624 2.0

RGMII IO Pad Set The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling. The libraries are compliant with the Gigabi...

1625 0.118

UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library...

1626 0.118

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...

1627 0.118

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library...

1628 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....

1629 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...

1630 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

1631 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

1632 0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

1633 0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

1634 0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1635 2.0

SD 3.0 I/O Pad Set The SD library provides the driver / receiver cell and required support cells for SD 3.0 signaling. Fault-tolerant operation. This library is offere...

1636 0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1637 0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1638 0.118

UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1639 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1640 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1641 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1642 0.118

UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35) UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)...

1643 0.118

UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35) UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)...

1644 0.118

UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm) UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)...

1645 0.118

UMC 0.18um Generic process MPCA core cell library UMC 0.18um Generic process MPCA core cell library...

1646 2.0

SSTL_15 IO Pad Set The SSTL_15 library supports bidirectional single-ended and differential SSTL_15 signaling. The driver/receiver pairs, with embedded power cells, are...

1647 0.118

UMC 90nm LL/RVT MPCA core cell library UMC 90nm LL/RVT MPCA core cell library...

1648 0.118

UMC 65nm SP/RVT Logic Process MPCA cell library UMC 65nm SP/RVT Logic Process MPCA cell library...

1649 0.118

UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming...

1650 0.118

UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4 UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4...