1701 2.0

2.5V 100MHz Oscillator Staggered I/O Pad Set The OSx_BI_032_12V oscillator is designed to generate an asynchronous on-chip clock signal with an appropriate external oscillator crystal. The design...

1702 0.118

UMC 55nm eHV process;Single-Port SRAM compiler UMC 55nm eHV process;Single-Port SRAM compiler...

1703 0.118

UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy...

1704 0.118

UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler. UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler....

1705 0.118

UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy. UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy....

1706 0.118

UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....

1707 0.118

UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....

1708 0.118

UMC 55nm ULP/LowK process Single-Port SRAM UMC 55nm ULP/LowK process Single-Port SRAM...

1709 0.118

UMC 55nm ULP process , Single-Port SRAM with row repair and HVT UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...

1710 0.118

UMC 55nm ULP/LowK process Single-Port SRAM UMC 55nm ULP/LowK process Single-Port SRAM...

1711 0.118

UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT...

1712 2.0

I2C IO Pad Set ...

1713 0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...

1714 0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...

1715 0.118

UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...

1716 0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...

1717 0.118

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...

1718 0.118

UMC 40nm Low Power Process , Two Port Register File with dual power rail UMC 40nm Low Power Process , Two Port Register File with dual power rail...

1719 0.118

UMC 55nm Standard Performance LowK Logic Process Two-Port Register File UMC 55nm Standard Performance LowK Logic Process Two-Port Register File...

1720 0.118

UMC 28nm HPC process Dual Port SRAM compiler UMC 28nm HPC process Dual Port SRAM compiler...

1721 0.118

UMC 28nm HPC process Dual Port SRAM with LVT UMC 28nm HPC process Dual Port SRAM with LVT...

1722 0.118

UMC 28nm HPC process Dual Port SRAM with row repair & LVT UMC 28nm HPC process Dual Port SRAM with row repair & LVT...

1723 2.0

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k Foundry Sponsored - Single Port SRAM compiler - TSMC 130 nm BCD - Memory optimized for ultra high density and high speed - compiler up to 64 k...

1724 2.0

LVDS IO Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...

1725 0.118

UMC 28nm HPC process Dual Port SRAM with row reapir UMC 28nm HPC process Dual Port SRAM with row reapir...

1726 0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...

1727 0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...

1728 0.118

40LP High density dual port SRAM compiler with Vss booster feature 40LP High density dual port SRAM compiler with Vss booster feature...

1729 0.118

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...

1730 0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...

1731 0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...

1732 0.118

UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode...

1733 0.118

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1734 0.118

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT...

1735 2.0

DDR3 / DDR4 Combo I/O Pad Set The DDR3 / DDR4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full compleme...

1736 0.118

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1737 0.118

UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1738 0.118

UMC 28nm HPC process Dual Port SRAM with Power gating UMC 28nm HPC process Dual Port SRAM with Power gating...

1739 0.118

UMC 28nm HPC process PG-Dual Port SRAM with LVT UMC 28nm HPC process PG-Dual Port SRAM with LVT...

1740 0.118

UMC 28nm HPC process PG Dual Port SRAM with LVT UMC 28nm HPC process PG Dual Port SRAM with LVT...

1741 0.118

UMC 28nm HPC Process dual port SRAM with power gating UMC 28nm HPC Process dual port SRAM with power gating...

1742 0.118

UMC 40nm LP process standard synchronous high density TCAM memory compiler. UMC 40nm LP process standard synchronous high density TCAM memory compiler....

1743 0.118

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...

1744 0.118

UMC 28HPC process standard synchronous high density TCAM memory compiler UMC 28HPC process standard synchronous high density TCAM memory compiler...

1745 0.118

UMC 55nm Logic process standard synchronous Contact ROM memory compiler. UMC 55nm Logic process standard synchronous Contact ROM memory compiler....

1746 2.0

LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full comp...

1747 0.118

UMC 55nm Logic process standard synchronous Contact ROM memory compiler. UMC 55nm Logic process standard synchronous Contact ROM memory compiler....

1748 0.118

UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler. UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler....

1749 0.118

UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler. UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler....

1750 0.118

UMC 55nm EFLASH Process Via ROM Memory complier UMC 55nm EFLASH Process Via ROM Memory complier...