1751 0.118

UMC 55nm ULP Low-K process HVT via1 ROM UMC 55nm ULP Low-K process HVT via1 ROM...

1752 0.118

UMC 55nm ULP/LowK Process via1 ROM compiler well bias UMC 55nm ULP/LowK Process via1 ROM compiler well bias...

1753 0.118

UMC 55nm ULP/LowK Process via ROM compiler for well bias UMC 55nm ULP/LowK Process via ROM compiler for well bias...

1754 0.118

UMC 40nm ultra low power via1 ROM complier UMC 40nm ultra low power via1 ROM complier...

1755 0.118

UMC 40nm uLP process ULL Via1 ROM compiler UMC 40nm uLP process ULL Via1 ROM compiler...

1756 0.118

UMC 28nm HPC Process PG Via ROM Compiler UMC 28nm HPC Process PG Via ROM Compiler...

1757 2.0

LVDS I/O Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...

1758 0.118

UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral...

1759 0.118

UMC 80nm LL/eHV Process synchronous Via ROM memory compiler UMC 80nm LL/eHV Process synchronous Via ROM memory compiler...

1760 0.118

UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler. UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler....

1761 0.118

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process 1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process...

1762 0.118

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type, 55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,...

1763 0.118

Fujitsu 90nm LL-UHS process MPCA M345 core cell library Fujitsu 90nm LL-UHS process MPCA M345 core cell library...

1764 0.118

Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)] Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]...

1765 0.118

UMC 55nm LP/LVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x005F_x005F_x000D_ UMC 55nm LP/LVT Logic Process MPCA cell library...

1766 0.118

UMC 55nm LP/RVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_ UMC 55nm LP/RVT Logic Process MPCA cell library...

1767 0.118

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony...

1768 2.0

ONFI_3 IO Pad Set The ONFI 3.0 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to suppor...

1769 0.118

UMC 0.11um CIS Process cell library UMC 0.11um CIS Process cell library...

1770 0.118

UMC 0.11um AL/LL Logic Process miniLib standard cell library UMC 0.11um AL/LL Logic Process miniLib standard cell library...

1771 0.118

HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D) HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)...

1772 0.118

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler. UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler....

1773 0.118

UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler. UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler....

1774 0.118

UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler. UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler....

1775 0.118

UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler....

1776 0.118

UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler. UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler....

1777 0.118

UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler....

1778 0.118

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler....

1779 2.0

ONFI_4 IO Pad Set The ONFI 4.0 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to suppor...

1780 0.118

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler....

1781 0.118

UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler...

1782 0.118

UMC 0.18UM Mixed Mode/RF; Two Port Register File UMC 0.18UM Mixed Mode/RF; Two Port Register File...

1783 0.118

HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM...

1784 0.118

UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler...

1785 0.118

UMC 90nm SPLVT ultra-high speed 1-port SRAM UMC 90nm SPLVT ultra-high speed 1-port SRAM...

1786 0.118

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler. UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....

1787 0.118

55 SP Dual Port SRAM compiler with 1P4M metal option 55 SP Dual Port SRAM compiler with 1P4M metal option...

1788 0.118

UMC 55nm eFlash Single-Port SRAM memory compiler UMC 55nm eFlash Single-Port SRAM memory compiler...

1789 0.118

UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier...

1790 2.0

RGMII / GMII Combo I/O Pad Set The (R)GMII libraries provide the combo driver / receiver and required support cells for (R)GMII signaling. The libraries are compliant with the Gigab...

1791 0.118

UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler...

1792 0.118

UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy...

1793 0.118

UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x005F_x005F_x005F_x005F_x000D_ UMC 55nm eFlash peocess One Port Register File memory compiler...

1794 0.118

UMC 55nm EFLASH Process Two Port Register File UMC 55nm EFLASH Process Two Port Register File...

1795 0.118

UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler...

1796 0.118

55nm eFlash Dual-Port SRAM memory compiler with row redundancy 55nm eFlash Dual-Port SRAM memory compiler with row redundancy...

1797 0.118

UMC 55nm eFlash process process ULL ROM Memory Compiler UMC 55nm eFlash process process ULL ROM Memory Compiler...

1798 0.118

UMC 55nm EFLASH Process ULL One Port Register File UMC 55nm EFLASH Process ULL One Port Register File...

1799 0.118

UMC 55nm eflash process , Two Port Register File memory compiler UMC 55nm eflash process , Two Port Register File memory compiler...

1800 0.118

UMC 55nm SST process standard synchronous high density single port SRAM memory compiler. UMC 55nm SST process standard synchronous high density single port SRAM memory compiler....