1801 2.0

3.3V 32 KHz RTC and Programmable 100MHz Oscillator I/O Pad Set The Oscillators library provides oscillators for on-chip asynchronous clock generation with an appropriate external crystal. This library is offered a...

1802 0.118

UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler. UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler....

1803 0.118

UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler. UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....

1804 0.118

UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_ UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...

1805 0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler. UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

1806 0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy. UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

1807 0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler. UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

1808 0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy. UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

1809 0.118

UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...

1810 0.118

UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...

1811 0.118

55ULP-SST 1P-RF with forward biased and HVT periphery 55ULP-SST 1P-RF with forward biased and HVT periphery...

1812 2.0

General-Purpose I/O (GPIO) - 1.5V-1.8V The 1.8V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog powe...

1813 0.118

55ULP-SST 1P-RF with forward biased and UHVT periphery 55ULP-SST 1P-RF with forward biased and UHVT periphery...

1814 0.118

UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler. UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler....

1815 0.118

UMC 55nm LP process with PG Dual port SRAM compiler UMC 55nm LP process with PG Dual port SRAM compiler...

1816 0.118

UMC 55nm ULP Low-K process One Port Register File for periphery HVT UMC 55nm ULP Low-K process One Port Register File for periphery HVT...

1817 0.118

UMC 55nm ULP process ROM compiler with HVT peripheral UMC 55nm ULP process ROM compiler with HVT peripheral...

1818 0.118

UMC 55nm ULP process PG-One Port Register File for periphery HVT UMC 55nm ULP process PG-One Port Register File for periphery HVT...

1819 0.118

UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT...

1820 0.118

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...

1821 0.118

UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell...

1822 0.118

UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell...

1823 2.0

3.3V Wide-Range General Purpose I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and space...

1824 0.118

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...

1825 0.118

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_ UMC 40nm LP Logic Process Ultra High Speed One-Port Register File...

1826 0.118

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating...

1827 0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...

1828 0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT...

1829 0.118

40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell...

1830 0.118

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell...

1831 0.118

UMC 40nm LP with power gating & peri-HVT 1PRF UMC 40nm LP with power gating & peri-HVT 1PRF...

1832 0.118

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler. UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....

1833 0.118

40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature 40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature...

1834 0.0

sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M Foundry sponsored - sROMet compiler - TSMC 55 nm HV - Non volatile memory optimized for high density and high speed - compiler range up to 2M...

1835 2.0

LVDS I/O Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...

1836 0.118

UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail...

1837 0.118

UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail...

1838 0.118

UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT...

1839 0.118

UMC 40nm uLP process ULL Single-Port SRAM UMC 40nm uLP process ULL Single-Port SRAM...

1840 0.118

UMC 40nm uLP process ULL One Port Register File memory compiler UMC 40nm uLP process ULL One Port Register File memory compiler...

1841 0.118

UMC 28nm HPC process Dual Port SRAM compiler UMC 28nm HPC process Dual Port SRAM compiler...

1842 0.118

UMC 28nm HPC process Dual Port SRAM compiler UMC 28nm HPC process Dual Port SRAM compiler...

1843 0.118

UMC 28nm HPC process Two Port Register File UMC 28nm HPC process Two Port Register File...

1844 0.118

UMC 28nm HPC process 2PRF with Bank2 UMC 28nm HPC process 2PRF with Bank2...

1845 0.118

UMC 28nm HPC process Two Port Register File with Bank2 UMC 28nm HPC process Two Port Register File with Bank2...

1846 2.0

ONFI_3 IO Pad Set The ONFI 3.0 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to suppor...

1847 0.118

UMC 28nm HPC process Two Port Register File with peri LVT UMC 28nm HPC process Two Port Register File with peri LVT...

1848 0.118

UMC 28nm HPC process Two Port Register File with LVT and Bank2 UMC 28nm HPC process Two Port Register File with LVT and Bank2...

1849 0.118

UMC 28nm HPC process Two Port Register File with LVT and Bank4 UMC 28nm HPC process Two Port Register File with LVT and Bank4...

1850 0.118

UMC 28nm HPC process One Port Register File with LVT UMC 28nm HPC process One Port Register File with LVT...