1951 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

1952 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

1953 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

1954 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 130 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1955 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 180 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1956 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 40ULP PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1957 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 55ULP PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1958 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 90 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1959 7.0

Standard cell cryogenic recharacterisation service for GF 22FDX to 4K operating temp Provides a cryogenic recharacterisation service for standard cells to operate down to 4K...

1960 7.0

Ultra Low Power Embedded SRAM on TSMC 16FFC PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

1961 0.0

ONFI4.0 NAND Flash IO in SMIC 40NLL, upto 800Mbps Brite ONFI IO is applied for NAND flash memory interface. Brite ONFI IO libraries are compliant to ONFI 5.0/4.2/4.0/3.2 standards with ODT (On-Die Ter...

1962 0.0

DDR combo IO in SMIC 55NLL, supporting DDR2/3/3L /LPDDR2/3, upto 1333Mbps Brite DDR IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200Mbps to 4805Mbps. Brite p...

1963 0.0

DDR combo IO in SMIC 28HKC+, supporting DDR3,4/LPDDR3,4, upto 2667Mbps Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1964 0.0

DDR combo IO in SMIC 40NLL, supporting DDR3,3U,3L,4/LPDDR2,3, upto 1866Mbps Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1965 0.0

DDR combo IO in SMIC 40NLL, supporting DDR2,3/LPDDR2,3, upto 1333Mbps Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1966 0.0

DDR combo IO in SMIC 28HKD 0.9/2.5V, supporting DDR2,3/LPDDR2,3, upto 1600Mbps for IOT application Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1967 0.0

DDR combo IO in SMIC 28HKD 0.9/2.5V, supporting DDR3,4/LPDDR3,4, upto 1866Mbps Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1968 0.0

TCAM in SMIC 28HK+ upto 800Mbps ...

1969 0.0

DDR combo IO in SMIC 28HKD 0.9/1.8V, supporting DDR3,4/LPDDR3,4, upto 2667Mbps Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...

1970 0.0

LVDS IO in SMIC 28HKC+, upto 1.6Gbps LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...

1971 0.0

LVDS IO in SMIC 40NLL, upto 800Mbps LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...

1972 0.0

PSRAM/SD3.0/EMMC5.1 IO in SMIC 28HKD 0.9/2.5V, upto 600Mbps ...

1973 0.0

2KByte EEPROM in SMIC 130EF ...

1974 100.0

TSMC GF LVDS Tx/Rx with optional CMOS I/O Flexible I/O cell for data and clock applications that supports differential (and optionally single-ended) Tx and Rx capabilities with no external com...

1975 100.0

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link Universal LVDS-based interfaces supporting variety of Tx and Rx configurations....

1976 0.0

8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process The ATO0008KX8MX180LBX4DA is organized as an 8K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in MXI- 0.1...

1977 2.0

Digital Cell Library GlobalFoundries The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-lea...

1978 2.0

Digital Cell Library Intel The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-lea...

1979 2.0

Digital Cell Library Samsung The agileDSCL is a compact digital standard cell library customisable for specific foundries and processes, and optimised for low-power, ultra-low-lea...

1980 2.0

Digital Cell Library SMIC The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-lea...

1981 2.0

Digital Cell Library UMC The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-lea...

1982 2.0

LVDS IO Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...

1983 2.0

General-Purpose I/O (GPIO) - 1.5V-1.8V The 1.8V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog powe...

1984 2.0

1.2V GPIO The 1.2V GPIO library provides a bidirectional I/O driver for Parallel Trace Interface applications. This cell is compliant with version 2.0 of the th...

1985 0.0

3.3V Wide-Range General Purpose I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spac...

1986 0.0

SD 3.0 I/O Pad Set The SD library provides the driver / receiver cell and required support cells for SD 3.0 signaling. Fault-tolerant operation. This library is offere...

1987 0.0

RGMII IO Pad Set The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling. The libraries are compliant with the Gigabi...

1988 0.0

3.3V Wide-Range General Purpose I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...

1989 2.0

I2C I/O Pad Set The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev. 4 of the I2Cbus industry specification. The design is compa...

1990 2.0

1.2V GPIO library designed for the SVID three-line interface. The 1.2V GPIO library provides an open-drain bi-directional I/O driver designed for the SVID three-line interface. It is compliant with the Intel SVID...

1991 2.0

I3C I/O Library The I3C library provides a bi-directional I/O driver designed for the I3C two-line interface. It is compliant with the MIPI Specification for I3C –Ver...

1992 2.0

1.8V General Purpose I/O Pad Set The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

1993 50.0

ONFI 3.2 NV-DDR2 PHY in GDSII Compliant to ONFI 3.2 electrical interface, Arasan ONFI 3.2 PHY, delivered in hard macro, is process technology proven and easy to integrate. This ON...

1994 100.0

ONFI 4.2 Controller Arasan Chip System’s (ACS) Open NAND Flash Interface (ONFI) Host Controller is designed to provide the next generation of high speed interaction with ...

1995 1.0

Programmable Special IO in SMIC0.13um AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...

1996 10.0

256x8 Bits OTP (One-Time Programmable) IP, TSM- 22ULP 0.8V/1.8V process The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- 22nm ULP CMOS...

1997 0.0

256x8 Bits OTP (One-Time Programmable) IP, TSM- 40G 0.9/1.8V Process The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- 40nm G standard...

1998 0.0

4Kx9 Bits OTP (One-Time Programmable) IP, Globa-Foundr--- 12LP+ 0.8V/1.8V Process The ATO0004KX9GF012LPP8ZA is organized as 4K-bits by 9 one-time programmable (OTP). This is a type of non-volatile memory fabricated in Globa-Foundr--...

1999 10.0

16Kx33 Bits OTP (One-Time Programmable) IP, TSM- 40LP 1.1V/2.5V Process The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ...

2000 10.0

768x39 Bits OTP (One-Time Programmable) IP, TSM- 55ULP 0.9V–1.2V / 2.5V Process The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 55nm LP 1.2V/2....