Design & Reuse
2715 IP
2501
0.0
1Kbyte EEPROM with configuration 64p8w16bit
180SMIC_EEPROM_08 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1 Kbyte (16(bit per word) x 8(words per p...
2502
0.0
1.25 Gbps LVDS IPs library
040TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Reference current/voltage source (...
2503
0.0
Up to 400 Mbps DDR LVDS receiver
130GF_LVDS_01 is a LVDS receiver with data rate up to 400 Mbps (DDR mode). The LVDS receiver converts input LVDS signal to differential CMOS 1.5V stan...
2504
0.0
36Kbyte EEPROM IP with configuration 32p32w288bit and oscillator
130GF_EEPROM_07 is a nonvolatile electrically erasable programmable read-only memory with volume 36Kbyte (32(bit per word) x 32(words per page) x 288(...
2505
50.0
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
2506
2.0
High-Speed LVDS (SERDES) Transceiver
High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS link...
2507
1.0
SMIC 0.18um High Density Standard Cell Library
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2508
1.0
SMIC 0.18um IO Library
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2509
1.0
SMIC 0.18um Single-Port/Two-Port Register File Compiler
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2510
1.0
SMIC 0.18um ROM Compiler
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2511
1.0
SMIC 0.15um High Density Standard Cell Library
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2512
1.0
SMIC 0.15um ROM Compiler
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2513
1.0
SMIC 0.15um Single-Port/Two-Port Register File Compiler
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2514
1.0
SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.15um LV High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.15um Lo...
2515
1.0
SMIC 0.25um High Density Standard Cell Library
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2516
1.0
SMIC 0.25um ROM Compiler
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2517
1.0
SMIC 0.25um Single-Port/Two-Port Register File Compiler
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2518
1.0
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The L...
2519
1.0
SMIC 0.15um SSTL2
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2520
1.0
SMIC 0.18um SSTL2
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2521
1.0
SMIC 0.15um SSTL3
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2522
1.0
SMIC 0.18um SSTL3
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2523
1.0
SMIC 0.13um 1.2~3.3V Voltage Controlled Crystal Oscillator
This IP is a tunable continuous Voltage Controlled Crystal Oscillator (VCXO). Its central frequency is 24.576 MHz. An analog voltage signal (VCTRL) ra...
2524
1.0
SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
2525
1.0
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA...
2526
1.0
SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, High ESD perfermance...
2527
1.0
SMIC 0.13um General Process, 1.2V/2.5V Standard I/O Library
VeriSilicon SMIC 0.13um 1.2V/2.5V I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SM...
2528
1.0
SMIC 0.13um General Process, 1.2V/3.3V Standard I/O Library
VeriSilicon SMIC 0.13um 1.2V/3.3V I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SM...
2529
1.0
SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
VeriSilicon SMIC 0.13um High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpora...
2530
1.0
SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
VeriSilicon SMIC 0.13um High-Vt High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International...
2531
1.0
SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM optimized for Semiconductor Manufacturing International Corporation (SMIC) 0...
2532
1.0
SMIC 0.13um Synchronous Diffusion ROM
VeriSilicon SMIC 0.13um Synchronous programmable diffusion ROM optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic...
2533
1.0
SMIC 0.13um High-Speed Synchronous Two-Port Register File
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8...
2534
1.0
VeriSilicon SMIC 0.18μm 1.8V/3.3V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2535
1.0
SMIC 0.13μm 3.3V Switchable Power Control Block
The present IP schemes a Voltage Detector (VDT) circuit. With the on-chip Bandgap reference, it detects the input voltage, i.e., VIN. It will output “...
2536
1.0
GSMC 0.15um 1.5V/3.3V PCI I/O Cells Library
VeriSilicon GSMC 0.15um 1.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...
2537
1.0
GSMC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon GSMC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18u...
2538
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (02) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing (GSMC) 0....
2539
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (03) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
2540
1.0
SMIC 0.13um 1.2V/2.5V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2541
1.0
SMIC 0.13um 1.2V/3.3V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/3.3V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2542
1.0
SMIC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon SMIC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMI...
2543
1.0
SMIC 0.18um SSTL_18 I/O
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2....
2544
3.0
Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compiler range up to 320 k...
2545
1.0
SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2546
1.0
SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
2547
1.0
GSMC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporatio...
2548
1.0
SMIC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon SMIC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Co...
2549
1.0
VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...
2550
1.0
VeriSilicon CHRT 0.13um 1.2V/3.3V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...