451 11.0

NVM Anti-Fuse OTP NeoFuse in Huali (55nm, 28nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

452 11.0

NVM Anti-Fuse OTP NeoFuse in HLIC (28nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

453 11.0

NVM Anti-Fuse OTP NeoFuse in HHNEC (55nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

454 11.0

NVM Anti-Fuse OTP NeoFuse in GLOBALFOUNDRIES (55nm, 40nm, 28nm, 22nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

455 11.0

NVM Anti-Fuse OTP NeoFuse in DongbuAnam (90nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

456 11.0

NVM Anti-Fuse OTP NeoFuse in UMC (110nm, 80nm, 55nm, 40nm, 28nm, 22nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

457 11.0

NVM Anti-Fuse OTP NeoFuse in TSMC (130nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N5A, N4P) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

458 0.3729

Thick oxide library - TSMC 90nm GT/G/LP_eF/LP Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

459 11.0

NVM OTP NeoBit in X-FAB (250nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

460 11.0

NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

461 16.0

On-chip protection against IEC61000-4-2 events ESD solutions and Analog Pads * All voltage domains (0.85V to 5.0V) * Additional higher voltage ranges in BCD processes * High ESD levels (scal...

462 11.0

NVM OTP NeoBit in SMIC (350nm, 180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

463 11.0

NVM OTP NeoBit in SKHYNIX (180nm, 130nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

464 11.0

NVM OTP NeoBit in Silterra (180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

465 1.0

Sony Camera LVDS Interface The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an exte...

466 6.0

LVDS 10 bits dual port transmitter ...

467 0.0

LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and ...

468 0.0

LVDS/FPD Link IP, Silicon Proven in GF 28LPe A physical layer IP for LVDS transmitter. This IP consists of 20-lane (4 x 4D1C) LVDS drivers and supports up to 1.5Gbps data rate. In LVDS mode, both...

469 0.3729

High Performance and High Density 10-track Standard cell library - TSMC 0.13um LV / LVOD / GS Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

470 0.0

V-by-One Tx IP, Silicon Proven in SMIC 40LL V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...

471 0.0

LVDS Rx IP, Silicon Proven in GF 28LPe A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is ...

472 2.0

Flash Memory LDPC LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...

473 0.118

Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler....

474 0.118

Two Port Register File Compiler IP, UMC 0.11um SP/AE process UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous Two Port SRAM memory compiler....

475 0.118

Dual Port SRAM Compiler IP, UMC 0.18um eFlash/G2 process UMC 0.18um eFlash GII Logic process high density Dual Port SRAM compiler....

476 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process UMC 40nm Logic process synchronous high density Dual Port SRAM memory compiler with redundancy....

477 0.118

Dual Port SRAM Compiler IP, UMC 55nm LP process UMC 55nm LP Logic process Synchronous Dual Port SRAM memory compiler....

478 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process UMC 55nm LP Logic process Synchronous Dual Port SRAM with redundancy feature....

479 0.118

Single Port SRAM Compiler IP, UMC 0.11um EEPROM process UMC 0.11um EE2PROM/LL 1.5V high density Single Port SRAM compiler....

480 0.3729

Thick oxide library - TSMC 0.13um LV / LVOD / GS Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

481 0.118

One Port Register File Compiler IP, UMC 0.11um HS/AE process UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process 1.41um2 cell One Port Register File memory compiler....

482 0.118

One Port Register File Compiler IP, UMC 0.11um HS/AE process UMC 0.11um AE eFlash HS process for One Port Register File compiler....

483 0.118

One Port Register File Compiler IP, UMC 0.11um LL/AE process UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process 1.41um2 cell Single Port Register File (One Port Register File) memory compiler....

484 0.118

One Port Register File Compiler IP, UMC 0.11um LL process UMC 0.11um AE/LL eFlash process One Port Register File....

485 0.118

One Port Register File Compiler IP, UMC 0.11um SP/AE process UMC 0.11um SP/AE Logic process Synchronous One Port Register File memory compiler with 1.41um2-Bit cell....

486 0.118

One Port Register File Compiler IP, UMC 0.13um CIS process UMC 130nm CMOS Image SensorCu process One Port Register File compiler....

487 0.118

One Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP/HVT Logic process with 6TSRAM (0.242 mm2) 1-port Register File memory compiler....

488 0.118

One Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP Logic process Single Port Register File memory compiler with LVT peripheral....

489 0.118

One Port Register File Compiler IP, UMC 55nm eFlash process UMC 55nm eFlash with peripheral HVT One Port Register File....

490 0.118

One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler....

491 0.3729

High Performance & High Density 10 - track Standard Cell library - TSMC 180nm LP/G Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

492 0.118

One Port Register File Compiler IP, UMC 55nm SP process UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler....

493 0.118

One Port Register File Compiler IP, UMC 90nm LL process UMC 90nm low leakage Low-K RVT process synchronous One Port Register File memory compiler....

494 0.118

Two Port Register File Compiler IP, UMC 0.11um LL process UMC 0.11um AE/LL eFlash process Two Port Register File....

495 0.118

Two Port Register File Compiler IP, UMC 0.11um HS/FSG process UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler....

496 0.118

Two Port Register File Compiler IP, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....

497 0.118

Two Port Register File Compiler IP, UMC 55nm LP process UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....

498 0.118

Two Port Register File Compiler IP, UMC 90nm SP process UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler....

499 0.118

ROM Compiler IP, UMC 0.11um LL process UMC 0.11um EE2PROM AE LL process Pcode ROM....

500 0.118

ROM Compiler IP, UMC 0.11um LL process UMC 0.11um AE/LL eFlash process Via1 ROM compiler....