51 0.118

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/FSG process 10bit 1MSPS SAR ADC with 8-to-1 Mux , UMC 0.11um HS/FSG Logic Process...

52 0.118

Ring Oscillator IP, Output: 32KHz, UMC 55nm LP process Internal-RC and Built-in Bandgap, trimmable fixed frequency 80MHz with trimming pad. Input 1.08V-1.32V, UMC 55nm Logic LP/RVT Low-K process...

53 0.118

A/D Converter IP, 10 bits, 54Msps, Pipelined, Single-end Input, UMC 55nm SP process 1.0V/3.3V 10Bits 54MSPS Single-end Input Pipelined ADC, UMC 55nm SP, LowK, Logic Process...

54 0.118

Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process Vrr=2.81V Vfr=2.81V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset,special request, UMC 55nm SP/RVT LowK Logic Process...

55 0.118

Band Gap IP, Input=1.0V-3.3V, VBG=0.75V with triming, Low power (1.8uW max, or 0.5uA@25C), UMC 55nm ULP process Input 1.0V-3.6V, VBG=0.75V, Band Gap, UMC 55nm ULP Low-K Logic process...

56 0.118

Linear Regulator IP, Input: 1.0V - 3.6V, Output: 0.9V/20mA, Standby Current: 0.8uA, UMC 55nm ULP process 1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process...

57 0.118

Linear Regulator IP, UMC 0.11um HS/AE process 3.3V to 1.2V Capacitor-Free Linear Regulator with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

58 0.118

Linear Regulator IP, UMC 0.18um G2 process Input 2.7V~3.6V, Output=1.8V,Loading 50mA Regulator, UMC 0.18um GII 1.8V/3.3V Process...

59 0.118

Band Gap IP, VBG=1.23V, UMC 0.35um process The FXBG010H80A is a complete bandgap voltage reference circuit with low temperature coefficient, and high power supply rejection ratio with output vo...

60 1.0

Wifi Receiver, 2402-2480 MHz - GlobalFoundries 22nm Wifi Receiver, 2402-2480 MHz - GlobalFoundries 22nm...

61 0.118

Linear Regulator IP, Output: 5V/50mA, UMC 0.35um process 5V with 50mA driving capability, Istb=124uA Linear Regulator, UMC 0.35um Logic process....

62 0.118

Power on Reset IP, Input: 3.3V, UMC 0.35um process Vrr=2.5V Vfr=2.3V, VCC=3.3V, Ivcc=18uA, Power On Reset, UMC 0.35um Logic process....

63 0.118

Linear Regulator IP, Output: 5V/150mA, UMC 0.35um process 5V with 150mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process....

64 0.118

Voltage Detector IP, Vdet: 2.55V, UMC 0.35um process Vdet=2.55V Vhys=0.05V, VCC=3.3V, Ivcc=35uA, UMC 0.35um Logic process....

65 0.118

A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process 10-Bit 300KSPS single End Analog-to-Digital converter, UMC 0.35um Logic process....

66 0.118

RC Oscillator IP, Output: 27.5MHz, UMC 0.35um Logic process 27.5MHz trimmable RC Oscillator, UMC 0.35um Logic process....

67 0.118

DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....

68 0.118

RC Oscillator IP, Output: 10KHz, UMC 0.35um Logic process Sub-low current with external-C, frequency 10KHz, VCCA=2.0V~3.3V, Ivcca<10uA....

69 0.118

Linear Regulator IP, Output: 5V/70mA, UMC 0.35um Logic process 5V with 70mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process....

70 0.118

PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process....

71 1.0

Programmable RF attennuator - GlobalFoundries 130nm RFSOI Programmable RF attennuator - GlobalFoundries 130nm RFSOI...

72 0.118

Voltage Detector IP, Vdet: 3.3V, UMC 0.5um process 5V/3.3V detector VDT, UMC 0.5um Logic process....

73 0.118

Power on Reset IP, Input: 5V, UMC 0.5um process Vrr=3.4V Vfr=3.0V, VCC=5V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process....

74 0.118

Power on Reset IP, Input: 3.3V, UMC 0.5um process Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process....

75 0.118

Power on Reset IP, Input: 3.3V, UMC 0.5um process Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, L type IO, Power On Reset, UMC 0.5um Logic process low voltage....

76 0.118

An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process. An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....

77 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process. Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

78 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

79 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process . Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

80 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

81 0.118

Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process. Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process....

82 1.0

Efuse Switch - GlobalFoundries 130nm RFSOI Efuse Switch - GlobalFoundries 130nm RFSOI...

83 0.118

Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process. Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process....

84 0.118

Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process. Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process....

85 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process. Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

86 0.118

Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40n...

87 0.118

Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm ...

88 0.118

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Pro...

89 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...

90 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...

91 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...

92 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...

93 1.0

SP4T RF switch - GlobalFoundries 130nm RFSOI SP4T RF switch - GlobalFoundries 130nm RFSOI...

94 0.118

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...

95 0.118

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Pr...

96 0.118

1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process 1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process...

97 0.118

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

98 0.118

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%. UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%....

99 0.118

Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process....

100 0.118

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...