851 2.0

Secure Digital I/O offerings Certus is pleased to offer Secure Digital compliant IOs in advanced technology nodes. Our SD IOs support DS, HS, SDR25, SDR50, DDR50 and SDR104 prot...

852 99.0

TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

853 0.0

TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

854 0.0

TSMC CLN20SOC 20nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

855 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

856 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

857 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

858 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

859 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

860 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

861 3.0

Linear regulator with ultra low quiescent current for retention applications Linear regulator with ultra low quiescent current for retention applications...

862 0.0

UMC L40G 40nm Clock Generator PLL - 680MHz-3400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

863 0.0

UMC L40G 40nm Clock Generator PLL - 340MHz-1700MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

864 0.0

UMC L40G 40nm Clock Generator PLL - 170MHz-850MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

865 0.0

UMC L40LP 40nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

866 0.0

UMC L40LP 40nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

867 0.0

UMC L40LP 40nm Clock Generator PLL - 75MHz-375MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

868 0.0

UMC L55LP 55nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

869 0.0

UMC L55LP 55nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

870 0.0

UMC L55LP 55nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

871 0.0

UMC L65LP 65nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

872 0.0

Linear Regulator, Low quiescent current The qLR-Aubrey-ref-[1.62-3.63]-[1.2-3.3]-I0.3-Iq200.01 is an ultra-low-quiescent-current regulator used to generate SoC internal supply for retention ...

873 0.0

UMC L65LP 65nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

874 0.0

UMC L65LP 65nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

875 0.0

GF L28HPP 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

876 0.0

GF L28HPP 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

877 0.0

GF L28HPP 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

878 0.0

GF L28SLP 28nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

879 0.0

GF L28SLP 28nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

880 0.0

GF L28SLP 28nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

881 0.0

GF L55G 55nm Clock Generator PLL - 360MHz-1800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

882 0.0

GF L55G 55nm Clock Generator PLL - 180MHz-900MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

883 3.0

Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode The RAR-eSR-qLR Retention Alternating Regulator combines two regulation sub-components: a high-efficiency switching regulator (eSR) and an ultra low q...

884 0.0

GF L55G 55nm Clock Generator PLL - 90MHz-450MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

885 0.0

12bit 200Msps High Speed Pipeline ADC IP Core High performance, 12-bit resolution, 200Msps sample rate Mixed-signal IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline networkin...

886 0.0

12bit 320Msps High Speed Pipeline ADC IP Core 12-bit resolution, 320Msps sample rate Mixed-signal IP, nodes up to 28nm Silicon proven. Leading edge systems on chip (SoCs) for wireline networking, ...

887 0.0

12bit 2Gsps High Speed Pipeline ADC IP Core High performance, 12-bit resolution, 2 Gsps sample rate Pipeline ADC IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline networking...

888 0.0

14bit 1.3Gsps High Speed Sigma Delta ADC IP Core High performance, 14-bit resolution, 1.3Gsps sample rate Sigma Delta IP core, nodes up to 28nm Silicon proven. Leading edge systems on chip (SoCs) for...

889 0.0

14bit 3.2Gsps High Speed Sigma Delta ADC IP Core High performance, 14-bit resolution, 3.2Gsps sample rate Mixed-signal Sigma Delta IP, nodes up to 28nm Silicon proven. Leading edge systems on chip (S...

890 0.0

12bit 160Msps Ultra low power SAR ADC IP Core 12-bit resolution, 160Gsps sample rate Mixed-signal Ultra low power SAR ADC IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline net...

891 50.0

16bit 5Msps SAR General Purpose ADC IP Core The ADC IP offers a resolution of 16 bits and a sample rate of 5Msps at nodes of 40nm Silicon Proven. These components enable cutting-edge systems on ...

892 0.0

12bit 4Gsps SAR General Purpose ADC IP Core High performance, 12-bit resolution, 4 Gsps sample rate Mixed-signal General Purpose ADC IP, nodes up to 8nm. Leading edge systems on chip (SoCs) for ...

893 0.0

12bit 500Msps High Speed General Purpose SAR ADC IP Core High performance, 12-bit resolution, 500 Gsps sample rate Mixed-signal General Purpose SAR ADC IP Core, nodes up to 8nm. Leading edge systems on chip ...

894 0.0

9bit upto 3Msps Ultra low power SAR ADC IP core High performance, 9-bit resolution, upto 3 Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for micr...

895 0.0

GF L55LP 55nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

896 0.0

10 bit 3Msps Ultra low power SAR ADC IP core High performance, 10-bit resolution, 3-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for microcon...

897 0.0

10bit 1Msps low power SAR ADC IP core High performance, 8-bit resolution, 1-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 95nm. Leading edge systems on ch...

898 0.0

10bit 100Ksps low power SAR ADC IP core High performance, 10-bit resolution, 100 Ksps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for microc...

899 0.0

12bit IQ High Speed 9.5bitENOB Ultra low power ADC IP Core High performance, 12-bit resolution, Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 7nm FinFET. Leading edge systems on chip (SoCs) fo...

900 0.0

12bit 1Msps low power SAR ADC IP core 12-bit successive approximation Analog-to-Digital Converter (ADC) is designed for high-performance applications. Utilizing 28FDSOI technology with pro...