4151 0.0

TSMC CLN65ULP 65nm DDR DLL - 126MHz-630MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4152 0.0

TSMC CLN65ULP 65nm DDR DLL - 80MHz-400MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4153 0.0

TSMC CLN65ULP 65nm DDR DLL - 60MHz-300MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4154 0.0

TSMC CLN40ULP 40nm DDR DLL - 88MHz-440MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4155 0.0

Power on Reset 1.2V 055SMIC_POR_04 provides a reset signal to the chip when supply voltage reach required level. POR generates reset signal depending of the level supply ...

4156 0.0

TSMC CLN40ULP 40nm DDR DLL - 56MHz-280MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4157 7.0

Ultra-Low Power 6 - 13 Bit 1-10 kS/s 1.9 μW SAR ADC The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regard...

4158 0.0

TSMC CLN40ULP 40nm DDR DLL - 42MHz-210MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4159 0.0

TSMC CLN40LP+ 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4160 0.0

TSMC CLN40LP+ 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4161 0.0

TSMC CLN40LP+ 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4162 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 347MHz-1735MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4163 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 220MHz-1100MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4164 8.0

Ultra-low jitter, low-power ring-oscillator-based PLL - 4.5GHz-9.5GHz InCirT’s APLL9GGF22 is the ring-oscillator based analogue-PLL which provides ultra-low jitter (690fs rms jitter at 9.5GHz) and low-power consumption (...

4165 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 165MHz-825MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4166 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4167 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4168 7.0

Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architect...

4169 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4170 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4171 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4172 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4173 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4174 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4175 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4176 0.0

TSMC CL016G 160nm DDR DLL - 120MHz-600MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4177 0.0

TSMC CL016G 160nm DDR DLL - 76MHz-380MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4178 0.0

TSMC CL016G 160nm DDR DLL - 57MHz-285MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4179 8.0

IGAPLLV01A, TSMC CLN16FF+LL Spread Spectrum Clock Generator PLL IGAPLLV01A is a Spread Spectrum Phase Lock Loop (SSPLL), without external components and is designed to provide stable and accurate clock. The IGAPL...

4180 0.0

GF L40LP 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4181 0.0

GF L40LP 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4182 0.0

GF L40LP 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4183 0.0

UMC L28HPC 28nm General Purpose PLL - 350MHz-1750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4184 0.0

TSMC CLN85LP 90nm General Purpose PLL - 120MHz-600MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4185 0.0

TSMC CLN65ULP 65nm General Purpose PLL - 100MHz-500MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4186 0.0

TSMC CLN40ULP 40nm General Purpose PLL - 75MHz-375MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4187 0.0

TSMC CLN40LP+ 40nm General Purpose PLL - 150MHz-750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4188 0.0

TSMC CLN28HPC+ 28nm General Purpose PLL - 360MHz-1800MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4189 0.0

TSMC CLN16FFCLL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4190 8.0

IGAPLLV03A, TSMC CLN16FF+ General Purpose PLL The IGAPLLV03A is a General purpose Phase Lock Loop (PLL), without external components and is designed to provide stable and accurate clock. The IGAPL...

4191 0.0

TSMC CLN16FF+LL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4192 0.0

TSMC CLN16FF+GL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4193 0.0

GF L40LP 40nm General Purpose PLL - 150MHz-750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4194 0.0

UMC L28HPC 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4195 0.0

UMC L28HPC 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4196 0.0

UMC L28HPC 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4197 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4198 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4199 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4200 0.0

TSMC CLN65ULP 65nm Clock Generator PLL - 200MHz-1000MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...