551 0.3729

DDRI/II/III SSTL/HSTL combo interface without RTT (square) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

552 0.118

SRAM/ROM Controller IP, SRAM/ROM Controller, Soft IP Static memory controller with AXI interface....

553 0.118

Single Port SRAM Compiler IP, UMC 0.11um LL/AE process UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process synchronous high density Single Port SRAM memory compiler....

554 0.118

Single Port SRAM Compiler IP, UMC 0.11um SP/AE process UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Single Port SRAM memory compiler....

555 0.118

Single Port SRAM Compiler IP, UMC 0.153um MS process UMC 0.153um Mixed-Mode/Logic process high density, Low Power mini Single Port SRAM....

556 0.118

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um CIS process UMC 0.18um CMOS Image Sensor process synchronous high density Single Port SRAM memory compiler....

557 0.118

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um MS process UMC 0.18um Mixed-Mode process synchronous high density Single Port SRAM memory compiler....

558 0.118

Single Port SRAM Compiler IP, UMC 0.25um Logic process UMC 0.25um Logic process synchronous high speed Single Port SRAM memory compiler....

559 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler....

560 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler with redundancy....

561 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port SRAM memory compiler....

562 0.3729

DDRI/II/III SSTL/HSTL combo interface with RTT (rectangle) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

563 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP/RVT+HVT Low-K Logic process synchronous high density Single Port SRAM memory compiler....

564 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process synchronous ultra high speed Single Port SRAM memory compiler....

565 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler....

566 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler with row-pair redundancy....

567 0.118

Single Port SRAM Compiler IP, UMC 65nm SP process UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM memory compiler....

568 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM with redundaycy memory compiler....

569 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process UMC 65nm LL/RVT Low-K process synchronous high density, Single Port SRAM compiler with the row redundancy....

570 0.118

Single Port SRAM Compiler IP, UMC 65nm LL process UMC 65nm LL/RVT Low-K Logic process 1-port high density memory compiler....

571 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process UMC 90nm SP/ Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy....

572 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process UMC 90nm SP/RVT Low-K Logic process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH)....

573 0.3729

DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

574 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process UMC 90nm LL/RVT Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy....

575 0.118

Single Port SRAM Compiler IP, UMC 90nm LL process UMC 90nm Logic process low leakage devices synchronous Low Power Single Port hihg density memory compiler....

576 0.118

Controller IP, SPI Flash controller, Soft IP Flash Controller with SPI Interface....

577 20.0

32/64-bit PC133 SDRAM Controller The 32/64-bit PC133 SDRAM Controller” controller handles PC133 SDRAM compatible memory devices attached to a 32 or 64 bit wide data bus. The cont...

578 9.0

32-bit SSRAM/PROM Controller The 32-bit SSRAM/PROM Controller IP cores is an 32-bit SSRAM/PROM/IO controller that interfaces external Synchronous pipelined SRAM, PROM, and I/O to ...

579 3.0

Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O...

580 1.0

QUAD SPI Memory controller The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly...

581 1.0

HBM3/2E Combo PHY&Controller The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architec...

582 1.0

HBM2E PHY&Controller Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....

583 0.3729

SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 65nm 65GP,LP,LP_EMF Dolphin s hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with...

584 1.0

HBM2E/2 Combo PHY&Controller Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized ...

585 1.0

HBM3/3E PHY & Controller This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...

586 1.0

ONFI IO 2.2 /5.0 The INNOSILICON IPTM Mixed-Signal ONFI PHYs provide Turnkey physical interface solutions for ICs requiring access to ONFI compatible NAND FLASH device...

587 30.0

NVM Express Host IP Core The IPM-NVMe_Host core is a verilog IP to be integrated in a FPGA or ASIC design. It fully manages the NVMe and PCIe protocol on the host side without...

588 30.0

create easily your own PCIe NVMe SSD This architecture proposal is based on NVMe and NAND Flash Controller offloaded IPs. It is integrated in a FPGA and could be also be integrated in ASI...

589 30.0

add encryption, compression ... in your datas This architecture proposal is based on NVMe offloaded IPs. It is integrated in a FPGA and could be also be integrated in ASIC, allowing to provide des...

590 2.0

NVME Host IP The new NVME-HOST-IP of Logic Design Solutions enables now random access in addition to the existing sequential access and multi-user access. FAT32 fi...

591 2.0

Artix Ultra Scale Plus NVMe Host IP Gen4 The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. - The LDS NVME HOST IP provides two interfaces : o One C...

592 80.0

Universal NVM Express Controller (UNEX) Mobiveil's Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions ...

593 50.0

PCIe Gen5 NVMe SSD RAMDISK Reference Platform Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...

594 0.3729

DDRI/II/III SSTL/HSTL combo interface without RTT (rectangle) - TSMC 65nm 65GP,LP,LP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

595 20.0

LPDDR4x/4 PHY IP for 22nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

596 15.0

LPDDR5X/5/4X/4 PHY IP for 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

597 20.0

LPDDR5X/5/4X/4 PHY for 16nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

598 20.0

LPDDR5X/5/4X/4 combo PHY at 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

599 0.0

Read-Modify-Write Core The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be ca...

600 0.0

Multi-Port Front-End The Rambus Multi-Port Front-End Core from Rambus provides a multi-port interface to Rambus Memory Controller Cores. Each user request is provided wit...