251 0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

252 0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

253 0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...

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Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...

255 0.118

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process...

256 0.118

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process. DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process....

257 0.118

compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....

258 0.3729

Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 5nm 5FF Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

259 0.118

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process ....

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DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process...

261 0.118

UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device...

262 0.118

40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage...

263 0.118

40nm LPDDR2-PHY command/address block for SIP 40nm LPDDR2-PHY command/address block for SIP...

264 0.118

40nm LPDDR2-PHY data block for SIP 40nm LPDDR2-PHY data block for SIP...

265 0.118

LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process...

266 0.118

40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process...

267 0.118

ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process...

268 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

269 0.3729

SDRAM DDR4/3/2 & LPDDR4/3/2 Hardened PHY - TSMC 6nm 6FF This product is under development....

270 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

271 0.118

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process...

272 0.118

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version...

273 0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

274 0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

275 0.118

DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...

276 0.118

DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...

277 0.118

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT...

278 0.118

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...

279 0.118

DDR3 RTL PHY Address Command module DDR3 RTL PHY Address Command module...

280 0.3729

Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 6nm 6FF Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

281 0.118

DDR3 RTL PHY data module DDR3 RTL PHY data module...

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Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces...

283 0.118

DDRx Bist Controller with I2C slave and multi-channel AMBA master DDRx Bist Controller with I2C slave and multi-channel AMBA master...

284 0.118

DFI Wrapper DFI Wrapper...

285 0.118

DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY...

286 0.118

Embedded flash controller The embedded flash controller (EFC) is flash memory device controlling apparatus and developed based on the Embedded Flash Macro (EFM) of pFusion co. ...

287 0.118

Flash Memory pre-fetcher controller with AHB lite system Flash Memory pre-fetcher controller with AHB lite system...

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Embedded flash controller for UMC 55LP Spit Gate embedded Flash. Embedded flash controller for UMC 55LP Spit Gate embedded Flash....

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Embedded synchronous single port SRAM/ROM memory controller with AXI slave port. Embedded synchronous single port SRAM/ROM memory controller with AXI slave port....

290 90.0

HBM2/2E Memory Controller Core The Rambus HBM2/2E Controller Core is designed for use in applications requiring high memory throughput, low latency and full programmability. The ...

291 0.3729

Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 12nm 12FFC,FFC+ Dolphin Technology s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2...

292 90.0

LPDDR4X / LPDDR4 Controller The Rambus LPDDR4X/4 controller core is designed for use in applications requiring high memory throughput at low power including mobile, Internet of ...

293 90.0

GDDR6 Memory Controller Rambus GDDR6 Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The ...

294 100.0

DDR4 Memory Controller Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmabilit...

295 100.0

DDR3 Memory Controller Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full progra...

296 100.0

HBM3E/3 Memory Controller The Rambus HBM3E/3 Controller Cores are designed for use in applications requiring high memory throughput, low latency and full programmability. T...

297 10.0

DDR5/4 PHY in Samsung (10nm, 8nm, 7nm) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

298 100.0

LPDDR5X DDR Memory Controller MEMTECH’ Olympus Mons-L Series LPDDR5X/LPDDR5 controller provide high-reliability, high-performance, low-latency, multi-port, multi-interface configur...

299 5.0

Frame Rate Converter for 4K TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which gen...

300 0.0

Up to 50% main memory bandwidth acceleration The Ziptilion Bandwidth IP accelertes the main memory bandwidth with up to 50%. The IP core packages a novel and proprietary technology that accelerat...