601 0.0

GLink AXI Wrapper GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...

602 0.0

GLink CXS-Bridge GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...

603 10.0

USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...

604 0.0

GLink Multi-Slice PCS GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...

605 0.0

TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4,SAS-3 G1-G4, SATA-...

606 0.0

TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G...

607 0.0

TSMC CLN5FF GLink 2.3LL Die-to-Die PHY IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...

608 0.0

TSMC CLN5FF GLink GPIO IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...

609 0.0

TSMC CLN5FF GLink 2.0 Die-to-Die PHY IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...

610 0.0

TSMC CLN7FF Lane-based 1.5 – 22.5 Gbps Enterprise Multi-Standard SerDes The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...

611 0.0

TSMC CLN5FF GLink-3D Die-to-Die Master PHY IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...

612 0.0

TSMC CLN7FF GLink-3D Die-to-Die Slave PHY IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...

613 0.0

USB 2.0 Audio Devices Design Platform The USB 2.0 Audio Design Platform is a complete, integrated solution, dedicated for USB based Audio Devices, like microphone and speakers. DCD’s Audio...

614 10.0

USB 2.0 nanoPHY in UMC (65nm) The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...

615 0.0

USB 2.0 Device Controller with ULPI interface The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI cont...

616 0.0

I2C Bus Interface - Master with FIFO The DI2CM-FIFO core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as: a master transmitter or master receive...

617 1.0

SMBUS & PMBUS Master/Slave controller The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Mast...

618 18.0

Die-2-die interfaces for chiplets Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...

619 5.0

MIPI-I3C HOST (SDR) MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...

620 5.0

MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...

621 0.0

MIPI CSI2 Receiver Interface The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...

622 5.0

MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1 MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...

623 10.0

SPD5118 Hub Controller IP The SPD5 Hub function controller IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sen...

624 20.0

LPDDR4/3, DDR4/3 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

625 10.0

USB 2.0 picoPHY in TSMC (40nm, 28nm) The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applicati...

626 60.0

DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

627 20.0

GDDR6 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

628 20.0

High Performance HBM, HBM3 Memory Controller OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

629 0.0

MIPI M-PHY (HS-G3) in GF 28LP The MXL-MPHY-G-28SLP is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be us...

630 0.0

MIPI D-PHY Universal IP in TSMC 28HPM The MXL-DPHY-MIPI-UNIVERSAL-T-028HPM is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Stan...

631 0.0

MIPI D-PHY Universal IP in SMIC 130nm The MXL-DPHY-UNIVERSAL-S-130 is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

632 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 110G The MXL-DPHY-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...

633 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 65LP The MXL-DPHY-DSI-TX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D...

634 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP The MXL-DPHY-CSI-2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

635 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 40LP The MXL-DPHY-CSI-2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

636 10.0

USB 2.0 picoPHY in UMC (40nm, 28nm) The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applicati...

637 0.0

MIPI M-PHY in SMIC 130nm The MXL-MPHY-S-130 is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

638 5.0

USB Power Delivery 3.1 Physical Layer CT20602 is a complete USB Power Delivery 3.1 Physical Layer. It also implements that part of the USB Power Delivery 3.1 Protocol Layer which are def...

639 8.0

ARINC 429 IP Core ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...

640 2.0

1.8V/3.3V Switchable GPIO With 5V I2C Open - Drain & Analog Cells in Samsung 11nm LPP SAMSUNG 11nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBUS open-drain cell, 5V OTP cell, 1...

641 5.0

SOF-Calibrated 48MHz USB Clock CT20101 extracts a precise 48MHz clock frequency underlying a USB 1.1 data stream. The device implements a loop that controls the output frequency o...

642 5.0

Low/Full Speed USB Billboard Controller The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device. It integrates all necessary infrastructures, including the CT201...

643 33.0

Ultra Low-Latency IP PCI-express Framework LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those in the financial secto...

644 11.0

Die-to-Die (D2D) Interconnect Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...

645 11.0

MIPI D-PHY ...

646 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

647 0.0

eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...

648 15.0

MIPI D-PHY Universal IP in TSMC 40LP for Automotive The MXL-DPHY-UNIVERSAL-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard fo...

649 0.0

224G Ethernet PHY IP for TSMC N3P The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

650 0.0

PCIe 4.0 PHY on 5nm The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...