851 0.0

112G-ULR PAM4 SerDes PHY for TSMC N6/N7 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

852 0.0

112G-ULR PAM4 SerDes PHY for TSMC N5/N4P 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

853 0.0

112G-ULR PAM4 SerDes PHY for TSMC N3E/N3P 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

854 0.0

112G-ULR PAM4 SerDes PHY for Samsung SF5A 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

855 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

856 0.0

112G-VSR for TSMC N3E/N3P 112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

857 0.0

112G-VSR for Rapidus 2nm 112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

858 0.0

56G-LR Pam4 SerDes for TSMC N6/N7 56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G The Cadence 56Gbps Long...

859 0.0

16G UCIe Standard PHY for TSMC N7 UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

860 0.0

16G UCIe Standard PHY for TSMC N5A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

861 0.0

16G UCIe Standard PHY for TSMC N4P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

862 0.0

16G UCIe Standard PHY for TSMC N3A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

863 0.0

16G UCIe Standard PHY for Samsung SF5A UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

864 0.0

16G UCIe Advanced PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

865 0.0

16G UCIe Advanced PHY for TSMC N4P/N5P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

866 35.0

MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+ The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting c...

867 0.0

32G UCIe Standard PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

868 0.0

40G Ultralink D2D PHY for TSMC N6, N7 Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

869 0.0

40G Ultralink D2D PHY for TSMC N5P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

870 0.0

40G Ultralink D2D PHY for TSMC N3P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

871 0.0

PHY for PCIe 5.0 and CXL for TSMC Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC is a high-performance SerDes operating from 1...

872 0.0

USB 2.0 PHY for Samsung 7LPP Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...

873 0.0

28G LR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 2...

874 0.0

32G LR Multi-Protocol SerDes (MPS) PHY Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure The 32G MPS...

875 0.0

16G Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...

876 0.0

PCIe 4/3/2 SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...

877 0.0

MIPI D-PHY Universal IP in TSMC 40ULP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

878 0.0

PHY for PCIe 7.0 and CXL for TSMC N3E/N3P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 7....

879 0.0

PHY for PCIe 6.0 and CXL for TSMC N4P/N5P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....

880 0.0

PHY for PCIe 6.0 and CXL for Samsung Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....

881 0.0

eUSB2V2 PHY Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...

882 0.0

30G MR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challengings applications The ...

883 0.0

PCI Express (PCIe) 7.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...

884 0.0

PCI Express (PCIe) 6.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...

885 0.0

USB 3.x PHY for TSMC Proven PHY IP for USB Device, Host, and DRD with small footprint and low active power The ubiquity of USB 3.x in devices makes it nearly mandatory fo...

886 10.0

UCIe D2D Adapter The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...

887 25.0

SerDes Hard Macro-IP in GlobalFoundries 22FDX Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well as...

888 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 28HPC+ The MXL-DPHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY...

889 0.0

CXL 3 Controller The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for...

890 0.0

MIPI D-PHY Receiver with PPI SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...

891 10.0

AMBA APB Target Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is desi...

892 10.0

Wishbone Target The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its go...

893 10.0

Avalon Target Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that ...

894 10.0

TileLink Target TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...

895 10.0

Bus Decoders Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus tr...

896 10.0

Bus Bridges Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of da...

897 10.0

Bus Convertors The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa. The downsizer module cuts the ...

898 10.0

Crossbars Interconnect An interconnect component connects initiators and targets in a system. A single initiator system simply requires a decoder and multiplexor, which are ...

899 10.0

MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display in...

900 38.0

UCIe Die-to-Die Controller GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UC...