951 0.0

16G Serdes in SMIC 28HKD 0.9/1.8V Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...

952 0.0

16G Serdes in SMIC 28HKD 0.9/2.5V Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...

953 0.0

12.5G Serdes in SMIC 40NLL Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...

954 10.0

USB 3.0 femtoPHY in Samsung (14nm, 11nm, 10nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

955 25.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX+-T028HPC+-RF-ULL is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification fo...

956 0.0

PCIE4 PHY in SMIC 28HKD 0.9/1.8V Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...

957 0.0

PCIE4 PHY in SMIC 28HKD 0.9/2.5V Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...

958 0.0

PCI Master/Target Interface Core ...

959 0.0

32-bit, 33 MHz Multifunction Target Interface The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...

960 0.0

32-bit/33,66Mhz PCI Host Bridge ...

961 0.0

AMBA AHB to APB Bus Bridge Core The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...

962 0.0

General-Purpose I/O Controller Core The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...

963 0.0

Internal Synchronous SRAM Controller Core The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...

964 0.0

Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...

965 5.0

MIPI I3C Basic Target The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...

966 100.0

MIPI D-PHY Universal IP in TSMC 22ULP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2....

967 10.0

I2C and SPI Master/Slave Controller The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Cir...

968 2.0

IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet offerings. Our I/O s...

969 3.0

Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain, SPI in TSMC 110nm This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this nod...

970 2.0

Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain in 110nm This silicon-proven Wirebond compatible library in Dongbu HiTek 110nm features a multi-voltage, multi-standard General Purpose Input Output with an Op...

971 2.0

A 65nm/55nm Wirebond IO Library with 1.2V to 3.3V GPIO and 5V ODIO Full Custom IO Library. Multi-voltage GPIO Library. Includes 5V Open-Drain; precision PWM Output, 1.2V to 3.3V GPIOs and Analog/RF IOs. Also include ...

972 3.0

<4Gbps Low Power D2D Interface Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...

973 2.0

Flipchip 5V Fail-Safe GPIO, 5V GPIO, 5V GPI and I2C Compliant 5V ODIO This flip-chip compatible library in Dongbu HiTek 130nm features a fail-safe GPIO, two standard GPIOs, a 5V GPI, and 5V I2C-compliant ODIO. The GFGPIO...

974 3.0

TSMC 22nm ULL Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO and 1.8V Analog Cell This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. Th...

975 3.0

TSMC 22nm ULL Wirebond/Flipchip I/O Library with switchable 1.8V/3.3V GPIO, 3.3V I2C ODIO, and 3.3V Analog Cell This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V durin...

976 3.0

Three-Speed Inline I/O Library with ODIO in TSMC 22nm This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. A...

977 25.0

MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-...

978 3.0

1.8V/3.3V flipchip I/O library with 4kV HBM ESD protection, I2C compliant ODIO This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...

979 3.0

A Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD pro...

980 3.0

1.8V/3.3V Flipchip I/O Library with 4kV HBM, I2C Compliant ODIO and 5V Hot-Plug Detect This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...

981 3.0

1.8V/3.3V Fail-Safe Multi-Voltage GPIO This silicon-proven TSMC 28nm Digital I/O Library delivers a high-performance, low-power interface solution designed for advanced digital applications...

982 3.0

A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions. This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and...

983 3.0

Inline Wirebond 1.8V to 3.3V Multi-Voltage GPIO with 5V Open-Drain I/O This I/O Libraru is a high-performance I/O solution for TSMC 22nm technology, supporting both digital and analog interfaces. Designed for 1.8V3.3V ope...

984 15.0

Interlaken Controller Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...

985 15.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

986 30.0

Universal Chiplet Interconnect Express (UCIe) Controller Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...

987 20.0

Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane * The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RI...

988 0.0

MIPI D-PHY 4 Lane CSI-2 TX (Transmitter) in TowerJazz 110nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

989 40.0

Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane * The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8...

990 15.0

Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane * The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...

991 0.0

Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane * The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data strea...

992 7.0

Display Controller - LCD / OLED Panels (AHB Bus) The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...

993 3.0

I2C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

994 0.0

RGB to CCIR 601 / 656 Encoder The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...

995 1.0

BitBLT Graphics Hardware Accelerator (AXI Bus) The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

996 1.0

BitBLT Graphics Hardware Accelerator (AHB Bus) The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...

997 0.0

BitBLT Graphics Hardware Accelerator (AXI4 Bus) The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

998 1.0

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...

999 10.0

MIPI D-PHY DSI TX+ (Transmitter) IP in Samsung 28FDSOI The MXL-DPHY-DSI-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, whic...

1000 3.0

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...