1101 0.118

USB 2.0 OTG PHY IP, UMC 55nm SP process OTG USB 2.0 PHY (VDT and ID are included in PHY), UMC 55nm SP Low-K Logic process....

1102 0.118

USB 2.0 OTG PHY IP, UMC 65nm SP process USB2.0 OTG (VDT and ID are included in PHY), UMC 65nm SP/HVT Low-K process....

1103 0.118

USB 2.0 OTG PHY IP, UMC 65nm LL process USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm low leakage RVT Low-K process....

1104 0.118

USB 2.0 OTG PHY IP, UMC 65nm LP process USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm LP/RVT Low-K Logic process....

1105 0.118

USB 2.0 OTG PHY IP, UMC 90nm SP process USB2.0 OTG PHY, UMC 90nm SP/RVT/ Low-K process....

1106 0.118

USB 2.0 OTG PHY IP, UMC 90nm LL process USB2.0 OTG PHY, UMC 90nm LL Low-K -RVT process 2.5V OD 3.3V....

1107 0.118

USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process USB3.0 PHY, UMC 0.11um HS/AE Logic process....

1108 0.118

USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process....

1109 0.118

USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process....

1110 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 22ULL The MXL-DPHY-CSI-2-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1111 0.118

USB 3.0 OTG PHY IP, UMC 55nm SP process USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process....

1112 0.118

USB 3.0 OTG PHY IP, UMC 90nm SP process USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process....

1113 1.0

MIPI C-PHY RX PHY The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...

1114 1.0

MIPI C-PHY DSI RX IP Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...

1115 1.0

MIPI C-PHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...

1116 1.0

MIPI C/D-PHY RX The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...

1117 1.0

MIPI C/D-PHY CSI-2 RX IP Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...

1118 1.0

MIPI DSI-2 DSC RX IP Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...

1119 1.0

MIPI CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1120 1.0

MIPI CSI-2 TX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1121 10.0

MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP The MXL-CDPHY-DSI-RX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...

1122 1.0

MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI) The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...

1123 1.0

MIPI C-PHY TX PHY The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...

1124 1.0

MIPI C/D-PHY TX The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...

1125 1.0

MIPI D-PHY TX The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

1126 1.0

MIPI D-PHY TX COMBO LVDS PHY The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...

1127 1.0

MIPI D-PHY TX Combo TTL PHY The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

1128 1.0

MIPI D-PHY_2.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1129 1.0

MIPI D-PHY_1.2G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1130 1.0

MIPI D-PHY_1.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1131 1.0

MIPI D-PHY_4.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

1132 20.0

MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+ The MXL-LVDS-DPHY-1p5G-CSI-2-RX-T-028HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Spe...

1133 1.0

MIPI D-PHY CSI-2 RX IP Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...

1134 1.0

MIPI D-PHY Combo LVDS CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...

1135 1.0

MIPI DPHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

1136 1.0

MIPI D-PHY DSI 1.2G RX IP Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...

1137 1.0

MIPI D-PHY DSI 1.5G RX IP Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...

1138 1.0

MIPI D-PHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

1139 1.0

MIPI D-PHY Combo LVDS DSI TX IP Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...

1140 1.0

MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI) The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...

1141 1.0

MIPI M-PHY TX/RX + Controller INNOSILICON M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of group of communication protocols defined by MIPI ...

1142 6.0

32-bit PCI Bus Master/Target 32-bit PCI Bus Master/Target with configurable FIFOs and AHB back end...

1143 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 55ULP The MXL-DPHY-DSI-TX-T-55ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...

1144 8.0

Bi-directional High speed interface lane up to 12.5Gbps InCirT offers SerDes which can deliver up to 12.5Gbps per lane for bidirectional data transfer. It consists of programmable receiver front-end and tra...

1145 1.0

64G/56G SerDes The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...

1146 1.0

JESD204B Controller JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...

1147 1.0

JESD204B PHY & Controller JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...

1148 1.0

5G Multi-SerDes For PCIe2.0/USB3.0 PHY The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the P...

1149 1.0

8G Multi-SerDes For PCIe3.0/USB3.0 PHY The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the P...

1150 1.0

PCIe2.0 PHY & Controller The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet,...