1201 1.0

HDMI2.0 TX Controller Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...

1202 1.0

HDMI2.0/1.4 TX PHY & Controller Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1203 1.0

HDMI2.0 TX PHY Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1204 1.0

HDMI2.1 TX Controller Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...

1205 1.0

HDMI2.1 TX PHY Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with ...

1206 1.0

HDMI2.1 Transmitter PHY & Controller Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1207 4.0

SAS Initiator Core The IntelliProp IPC-SS105A-HI SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high...

1208 4.0

SAS Target Core The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to connect to high throu...

1209 4.0

SATA "Y" RAID Bridge without NCQ The IntelliProp IPP-SA112A-BR SATA “Y” Bridge with RAID design provides SATA compliant connections and a standard SATA interface that performs RAID0 t...

1210 60.0

MIPI D-PHY IP 4.5Gbps in TSMC N7 The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

1211 4.0

SATA Host App Core IntelliProp’s SATA host core (IPC-SA101A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables host application companies to ...

1212 4.0

SATA RAID Core The IntelliProp IPC-BL109A-RD SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide higher performance a...

1213 4.0

SATA "Y" Bridge The IntelliProp SATA "Y" Bridge design (IPP-SA111A-BR) provides SATA compliant connections per SATA-IO 3.3 and a standard SATA interface to access dri...

1214 4.0

SATA Device ADCI Core IntelliProp’s SATA Device ADCI core (IPC-SA155A-DT) is an industry standard Serial-ATA (SATA) device interface core that allows companies to build hig...

1215 4.0

SATA 1-to-1 Speed Bridge with Sandbox The IntelliProp SATA 1-to-1 Speed Bridge with Sandbox (IPP-SA110A-BR) design provides SATA compliant connections to a SATA host and a SATA device. The...

1216 1.0

25G Multi-SerDes PHY The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...

1217 1.0

12.5G Multi-SerDes PHY The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...

1218 1.0

10G Multi-SerDes PHY The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...

1219 1.0

32G Multi-SerDes For PCIe5.0/USB3.x PHY The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...

1220 6.0

Mil-Std-1553B/AS15531 Interface The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus ...

1221 11.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...

1222 6.0

Highly configurable high-speed serial link controller The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement: * SpaceFibre controller (GRSPFI) * W...

1223 1.0

V-By-One Receiver_8ch Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is co...

1224 1.0

Video-by-One Receiver IP_16ch This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for re...

1225 1.0

Video-by-One Transmitter IP_8ch Innosilicon VBO TX IP is designed for transmitting video data from a video source device to a display device. It is compatible with V-By-One HS 1.4 st...

1226 1.0

LVDS RX PHY & Controller Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...

1227 1.0

LVDS TX Combo TTL PHY Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...

1228 1.0

LVDS TX PHY & Controller Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...

1229 1.0

V-By-One PHY & Controller (Tx+ Rx) Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is co...

1230 2.0

I2C MAster Slave The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...

1231 2.0

I2C Master The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...

1232 0.0

AHB Low Power Subsystem - ARM M0 The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...

1233 2.0

I2C Slave The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...

1234 2.0

SATA HOST Synchronous IP The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1235 2.0

Serial ATA Dual Host Controller The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...

1236 2.0

SATA Host controller on Virtex 5 FXT The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1237 2.0

Dual SATA Host controller on Virtex 5 FXT FPGA The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...

1238 2.0

SATA Host Controller The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...

1239 2.0

SATA Host Controller on Spartan 6 LXT FPGA The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...

1240 2.0

SATA Host Controller on Virtex 6 LXT The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...

1241 2.0

SATA III HOST Controller on Virtex 6 The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...

1242 2.0

SATA Host on Altera Arria II GX The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...

1243 0.0

AHB Performance Subsystem - ARM M3 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...

1244 2.0

SATA Device Controller on Altera Arria II GX The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...

1245 2.0

SATA HOST Controller on Cyclone IV GX The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...

1246 2.0

SATA Device on Stratix IV GX The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...

1247 2.0

SATA Device on Virtex 6 The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...

1248 2.0

SATA RECORDER ON VIRTEX 6 The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...

1249 0.0

FPGA Proven PCIe GEN6 Controller PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...

1250 0.0

PCIe GEN6 PHY Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...