Design & Reuse
1878 IP
201
0.0
HDMI 2.1 Rx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The HDMI V2.1 Rx provides a complete single-link HDMI receiver function complies with HDMI specification version 2.1 It consists of two modules, a phy...
202
0.0
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
(PCIe 3.1) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input...
203
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the sup...
204
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the sup...
205
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with PCIe 3.0 Base Specific...
206
2.0
SATA RECORDER ON VIRTEX 7 GTX
...
207
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 14SFP
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...
208
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP integrates mixed signal cir...
209
0.0
PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 Base Specification. C...
210
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits t...
211
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base speci...
212
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
PCIe Gen 2 PHY IP is a physical layer (PHY) IP solution for consumer electronics, that allows for a full featured customization and complies with the ...
213
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customizati...
214
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to f...
215
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mi...
216
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...
217
0.0
AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
218
2.0
LDS SATA RECORDER ON ZYNQ
...
219
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0...
220
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 14SF+
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
221
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
222
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
The USB 2.0 PHY IP Core is a complete solution for the physical layer (PHY) that prioritizes both high performance and low power consumption. This ver...
223
0.0
USB 3.0 PHY IP, Silicon Proven in UMC 40SP
A Universal Serial Bus (USB) transceiver is available for peripheral devices. The PHY complies with the USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UT...
224
0.0
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data connection while using...
225
0.0
USB 3.0 PHY IP, Silicon Proven in SMIC 14SF+
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered. The PHY complies with the UTMI, USB 2.0 PIPE, and USB 3.0 (USB SuperSpeed)...
226
0.0
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
It supports both USB 3.1 Gen1 and Gen2 with this PHY IP. By offering a complete on-chip physical transceiver solution with built-in jitter injection, ...
227
0.0
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
With this PHY IP, it supports both USB 3.1 Gen1 and Gen2. By providing an integrated self-test module, a whole on-chip physical transceiver solution w...
228
0.0
USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps. It conforms with the standards of UTMI+ a...
229
2.0
LDS SATA RECORDER IP ON ARTIX 7
...
230
0.0
USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support of PIPE v4.4 interfa...
231
0.0
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It support...
232
0.0
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 40LL
The combined PHY complies with the PIPE, Serial ATA, PCIe, USB, USB 3.0, USB 2.0, and PCIe Peripheral Component Interconnect Express interface protoco...
233
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 40LP
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0 trans...
234
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
The USB 2.0 PHY IP Core offers a complete physical layer (PHY) solution for high performance and low power. It implements a High-Speed USB 2.0 transce...
235
0.0
USB 3.0 PHY IP, Silicon Proven in UMC 28HPC
For peripheral devices, there is a Universal Serial Bus (USB) transceiver available. The USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI standards ar...
236
0.0
MIPI CSI-2 Receiver v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destinati...
237
0.0
MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destinati...
238
0.0
MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro
Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low...
239
0.0
MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS
UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobile device. UniPro allo...
240
2.0
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
241
0.0
MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY
MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol. It supports video and command displays and can work in...
242
0.0
MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specification, and Universal ...
243
0.0
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal ...
244
0.0
MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specificatio...
245
60.0
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and D...
246
0.0
MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core. Supported protocols include the Display Serial I...
247
0.0
MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification. It is compatible with the MIPI Camera Serial Interface (C...
248
0.0
HDMI 2.1 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The HDMI V2.1 Tx complies with version 2.1 of the HDMI specification and offers a full single-link HDMI transmitter capability. It is made up of two m...
249
0.0
HDMI 2.1 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The HDMI V2.1 Rx complies with version 2.1 of the HDMI specification and offers a full single-link HDMI receiver function. It is made up of two module...
250
0.0
HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
IP solutions for HDMI Transmitter (TX) devices are compliant with HDMI 2.0 and 1.4 specifications and offer the essential logic to create and validate...