351 7.0

USB 2.0 High/Full-Speed Device Core The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functional...

352 0.118

MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process...

353 0.118

MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process...

354 0.118

MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process...

355 0.118

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process...

356 0.118

MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process...

357 0.118

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC process MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC process...

358 0.118

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process...

359 0.118

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process...

360 0.118

PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process....

361 0.118

UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES...

362 7.0

USB 2.0 High/Full/Low-Speed Embedded Host Controller The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functional...

363 0.118

UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES...

364 0.118

28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process 28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process...

365 0.118

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit...

366 0.118

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process...

367 0.118

USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process...

368 0.118

USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process...

369 0.118

USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF...

370 0.118

USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process...

371 0.118

USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process...

372 0.118

USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process...

373 7.0

USB 2.0 OTG High/Full/Low-Speed Dual Role Core The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...

374 0.118

Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process. Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process....

375 0.118

USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process...

376 0.118

USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process...

377 0.118

28nm HPC USB3.1 gen2 PHY(10Gbps) 28nm HPC USB3.1 gen2 PHY(10Gbps)...

378 0.118

28nm HPC+ USB3.1 gen2 PHY(10Gbps) 28nm HPC+ USB3.1 gen2 PHY(10Gbps)...

379 0.118

Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process....

380 0.118

PCIe Gen4 x8 Lane Endpoint Controller PCIe Gen4 x8 Lane Endpoint Controller...

381 0.118

V-by-One Receiver Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process....

382 0.118

MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process_x005F_x005F_x005F_x005F_x005F_x000D_ MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process...

383 0.118

MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process...

384 7.0

USB 2.0 OTG Full/Low-Speed Dual Role Core The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...

385 0.118

CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process...

386 0.118

MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process...

387 0.118

MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process...

388 0.118

28nm HPC x4 lane 10 Gbps SERDES 28nm HPC x4 lane 10 Gbps SERDES...

389 0.118

Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process...

390 0.118

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process...

391 0.118

USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x005F_x005F_x005F_x005F_x000D_ cost down from FZOTG266HJ0C_A USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A...

392 0.118

USB 2.0 On-The-Go PHY; UMC 28nm HLP Process USB 2.0 On-The-Go PHY; UMC 28nm HLP Process...

393 0.118

ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process...

394 0.118

USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...

395 10.0

SD 4.1 SDIO 4.1 Host Controller IP The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...

396 0.118

The PCIe Gen3 PCS for 28nm programmable serdes. The PCIe Gen3 PCS for 28nm programmable serdes....

397 0.118

V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller). V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller)....

398 0.118

Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output finally. Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output finally....

399 0.118

V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller). V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller)....

400 0.118

FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...