www.eetimes.com, Aug. 26, 2021 –
Is entirely autonomous chip design possible? Can AI behave as an "artificial architect," designing and optimizing entire chips?
This is the question Synopsys CEO Aart de Geus set out to answer in his keynote presentation at Hot Chips. The answer is a resounding "yes".
Synopsys has long been working on using AI in its EDA tools (according to De Geus, all Synopsys tools today use AI in one form or another). Its flagship AI-powered tool, DSO.ai, launched last year. DSO tackles all the tasks in the geometry of chip design, that is, all the physical aspects of the design, in contrast to some other AI-based tools which tackle bits of this task only. DSO is named for design space optimization, Synopsys' vision of the next step in today's design space exploration process.
The size of the task cannot be underestimated – the search space for place and route alone is 10 to the power of 90,000, orders of magnitude greater than the search space for the fiendishly complicated Chinese game of Go at 10 to the power of 360.
Synopsys' technology is based on a technique called reinforcement learning – a version of deep learning that doesn't require a massive influx of data. Instead, the system starts from zero, designing chips randomly, and is given a score each time for how well it does. Over time, it designs many, many chips by trial and error and tries to optimize its score, effectively learning chip design from scratch. This technique means Synopsys doesn't have to have access to huge amounts of data (in this case, chip designs, which are its customers' IP) to train its algorithms.