eenewseurope.com, Oct. 25, 2024 –
In its first project, the UK wing of Belgian R&D lab imec is developing a tool to optimise the energy of next generation AI chips across compute, memory and connectivity.
imec UK in Cambridge has been funded by the UK's Advanced Research and Invention Agency (ARIA) with £3m (€3.6m) to develop a predictive system-level software framework for training of large AI models.
The simulation tool will use existing component models and add in new technologies such as CFETs to boost research into hardware and technology for AI training using system technology co-optimisation (STCO).
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Current design space exploration (DSE) frameworks have primarily targeted AI inference, but the exponential growth of machine learning applications calls for more efficient AI training processes. This is time-consuming and involves large compute
infrastructure that results in high operating and energy costs.
The system optimisation tool aims to address power/thermal limits, memory constraints and bandwidth bottlenecks to achieve optimal energy usage.
"We will be able to create a robust DSE framework that can be used in early-stage explorations of optimal system and technology configurations for AI training, thereby validating or
motivating new technology specifications," said James Myers, program director STCO at imec Cambridge UK. "The new DSE will leverage established component-level simulators available in the academic community that will be augmented with emerging technology models such as short-range optical interconnects or future nanosheet and CFET CMOS nodes."