SiPearl, the company building the high-performance low-power European microprocessor for HPC(1) and AI inference, unveils the key features of Rhea1, its firstgeneration product. To meet all the requirements for HPC and AI inference workloads with best-in-class energy-efficiency, Rhea1 will integrate:
sipearl.com/, May. 13, 2024 –
- 80 arm® Neoverse V1 cores with 2 Scalable Vector Extension (SVE) units of 256
- bits per core,
- built-in High Bandwidth Memory with 4 stacks of HBM,
- 4 DDR5 interfaces.
Maisons-Laffitte (France), May 13, 2024 – Attending ISC tradeshow in Hamburg (booth
#L22), SiPearl, the company building the high-performance low-power European microprocessor for HPC and AI inference announces the main features of Rhea1, its firstgeneration microprocessor.
Designed with high-performance energy-efficient arm® Neoverse V1 platform, Rhea1 will include in a single package:
- 80 arm® Neoverse V1 cores ensuring high compute performance and efficient performance per watt. Each core includes 2 Scalable Vector Extension (SVE) of 256 bits each, enabling fast vector computations while optimizing area and energy use;
- Built-in High Bandwidth Memory, with 4 stacks of HBM, to provide a balanced solution ideal for HPC, big data and AI Inference applications, which are often memory bandwidth bound;
- 4 DDR5 interfaces supporting 2 DIMMs Per Channel (2DPC);
- 104 lanes of PCIe Gen5 interface: up to 6 x16 lanes + 2 x4 lanes;
- High-performance arm® Neoverse CMN-700 Coherent Mesh Network on Chip (NoC) to
- interconnect compute and I/O elements;
- Support for Flat or Quadrant mode.
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