SAN JOSE, Calif. , Feb. 21, 2018 – Cadence Design Systems, Inc. (NASDAQ:
CDNS) today announced it will showcase the Cadence® Verification Suite and its most recent innovations at DVCon 2018. The event is being held from February 26 to March 1, 2018 in San Jose, Calif., with Cadence, a gold sponsor, in booth 702. To register for the conference, visit
https://dvcon.org/.
WHAT: Cadence and its customers are scheduled to deliver several presentations for the DVCon attendees. The speaking sessions are as follows:
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Accellera Tutorial: Portable Test and Stimulus: The Next Level of Verification Productivity Is Here, Monday, February 26 at 9:00 a.m., Sharon Rosenberg, Senior Solutions Architect
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Accellera Tutorial: IEEE-Compatible UVM Reference Implementation and Verification Components, Monday, February 26 at 2:00 p.m., Uwe Simm, Software Architect
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Cadence Tutorial: SoC Verification Speed–More Is Better, Thursday, March 1 at 8:30 a.m., Adam Sherer, Product Management Group Director
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Lunch Panel: Smarter and Faster Verification: Beyond Brute Force, Thursday, March 1 at 12:15 p.m., Larry Melling, Senior Product Management Director
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Cadence Tutorial: Making Cars Safer–One Chip at a Time, Thursday, March 1 at 2:00 p.m., Ann Keffer, Product Marketing Director
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