A paper from researchers at Samsung describing a 3nm CMOS IC manufacturing process with gate-all-around (GAA) transistors, has been accepted as a late paper at the upcoming International Electron Devices Meeting (IEDM).
San Francisco, California, Nov. 07, 2018 –
IEDM takes place December 1 to 5 in San Francisco, California.
Samsung had announced earlier this year that its 3nm process will come in two variants – 3GAAE and 3GAAP – standing for early and plus and will be based on the nanosheet construction with multiple (three) lateral ribbon-shaped wires in a fin (see Samsung to introduce nanosheet transistors in 3nm node ).
According to the paper abstract the GAA transistor channels comprising the horizontal nanosheets that are completely surrounded by gate structures. Samsung calls this a Multi-Bridge-Channel (MBC) architecture, and says it is highly manufacturable as it makes use of approximately 90 percent of the company's existing FinFET fabrication technology, requiring only a few revised photomasks.
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