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Faraday Technology

Hsinchu City, 300

Taiwan

About Faraday Technology

Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.

Analog & Mixed Signal->A/D Converter (ADC)->10-Bit ADC (49)

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/FSG process

A/D Converter IP, 10 bits, 54Msps, Pipelined, Single-end Input, UMC 55nm SP process

A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process

1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process

1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process_x005F_x005F_x005F_x000D_

10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process

10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process

10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process

10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process

10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process

10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process

A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process

A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process

A/D Converter IP, 10 bits, 10Msps, UMC 0.18um G2 process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, SAR type, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.13um LL/FSG process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.13um LL/FSG process

A/D Converter IP, 10 bits, 1Msps, UMC 0.13um LL/FSG process

A/D Converter IP, 10 bits, 1Msps, UMC 0.153um SP process

A/D Converter IP, 10 bits, 40Msps, UMC 0.162um SP process

A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Logic/Mixed-Mode process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.18um G2 process

A/D Converter IP, 10 bits, 80Msps, UMC 0.18um Logic/Mixed-Mode process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 55nm SP process

A/D Converter IP, 10 bits, 1Msps, UMC 65nm LL process

A/D Converter IP, 10 bits, 40MHz, UMC 90nm LL process

A/D Converter IP, 10 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process

A/D Converter IP, 10 bits, 10Msps - 50Msps, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 10Msps - 50Msps, UMC 90nm SP process

A/D Converter IP, 10 bits, 10Msps, SAR type, Differential inputs, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 10Msps, SAR type, Differential inputs, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 167Ksps, UMC 55nm LP process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 1Msps, UMC 0.18um G2 process

A/D Converter IP, 10 bits, 1Msps, UMC 40nm LP process

A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 55nm LP process

A/D Converter IP, 10 bits, 1Msps, SAR type, with 8-to-1 input MUX, UMC 55nm SP process

A/D Converter IP, 10 bits, 30Msps, UMC 0.25um Logic process

A/D Converter IP, 10 bits, 80Msps, UMC 0.11um HS/AE process

A/D Converter IP, 10 bits, 80Msps, UMC 40nm LP process

A/D Converter IP, 10 bits, 167Ksps, HJTC 0.18um eFlash/G2 process

A/D Converter IP, 10 bits, 167Ksps, UMC 55nm SP process

A/D Converter IP, 10 bits, 1Msps, HJTC 0.18um eFlash/G2 process

A/D Converter IP, 10 bits, 1Msps, UMC 0.18um G2 process

A/D Converter IP, 10 bits, 2Msps, with 2-to-1 input MUX, UMC 55nm SP process

A/D Converter IP, 10 bits, 500Ksps, HJTC 0.18um eFlash/G2 process

A/D Converter IP, 10 bits, 50Msps, UMC 40nm LP process

A/D Converter IP, 10 bits, 45Msps, UMC 40nm LP process

Analog & Mixed Signal->A/D Converter (ADC)->11-Bit ADC (3)

A/D Converter IP, 11 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process

A/D Converter IP, 11 bits, 1Msps, UMC 90nm LL process

A/D Converter IP, 11 bits, 1Msps, with 8-to-1 input MUX, HJTC 0.18um eFlash/G2 process

Analog & Mixed Signal->A/D Converter (ADC)->12-Bit ADC (11)

12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process

12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)

12Bit 1Msps SAR-ADC based on UMC 55nm uLP process

Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process

A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process

a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated

a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process

A/D Converter IP, 12 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process

A/D Converter IP, 12 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/AE process

A/D Converter IP, 12 bits, 80Msps, I-Q Channels, UMC 55nm SP process

A/D Converter IP, 12 bits, 1Msps, with 8-to-1 input MUX, UMC 55nm LP process

Analog & Mixed Signal->A/D Converter (ADC)->24-Bit ADC (3)

A/D Converter IP, 24 bits, 96KHz, UMC 55nm SP process

A/D Converter IP, 24 bits, Audio ADC, UMC 55nm SP process

A/D Converter IP, 24 bits, 96KHz, 3-channel, HJTC 0.18um eFlash/G2 process

Analog & Mixed Signal->A/D Converter (ADC)->6-Bit ADC (3)

A/D Converter IP, 6 bits, 85Ksps, UMC 0.162um G2 process

A/D Converter IP, 6 bits, 44Msps, UMC 0.18um Mixed-Mode process

A/D Converter IP, 6 bits, 44Msps, UMC 0.25um MS process

Analog & Mixed Signal->A/D Converter (ADC)->8-Bit ADC (3)

A/D Converter IP, 8 bits, 160Msps, UMC 0.11um HS/AE process

A/D Converter IP, 8 bits, 70Ksps, UMC 40nm LP process

A/D Converter IP, 8 bits, 70Ksps, UMC 55nm SP process

Analog & Mixed Signal->A/D Converter (ADC)->Other (6)

UMC 55uLP_x005F_x005F_x005F_x000D_ ADC

24bit 96KHz A/D converter, 1.8V 3-channel Sigma-Delta Audio ADC; HJTC 0.18um eFlash process

125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process_x005F_x005F_x005F_x000D_

0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process

1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS

A/D Converter IP, 18 bits, 96Ksps, UMC 0.25um Logic process

Analog & Mixed Signal->Amplifier-> (2)

An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process

5V 1W Mono Speaker Amplifier, UMC 55nm SP/RVT LowK Logic Process.

Analog & Mixed Signal->Analog Comparator-> (1)

Analog Comparator; 0.25um Logic process

Analog & Mixed Signal->Analog Front Ends-> (5)

Analog Front End IP for CMOS image processing applications

OFDM AFE using UMC 55nm eFlash Process

OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process

OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process

FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_

Analog & Mixed Signal->Clock Synthesizer-> (10)

Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process

IP name: FXS2D101HH0L Area: 300um*300um

Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.

Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.

Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process

Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process

NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x005F_x005F_x000D_

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process

Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process

Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.

Analog & Mixed Signal->Coder/Decoder (CODEC)-> (31)

UMC 28nm high performance stereo audio codec with highly integrated analog functionality system

UMC 40nm high performance mono audio codec with highly integrated analog functionality system

Audio ADDA IP, 16 bits, 96KHz, UMC 0.18um G2 process

Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process

Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process

Audio ADDA IP, 6 bits, 4MHz, UMC 0.18um G2 process

Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process

Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.11um HS/FSG process

Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.13um LL/FSG process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.13um LL/FSG process

Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process

Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process

Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process

Audio ADDA IP, 16 bits, Audio Codec, UMC 0.162um G2 process

Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process

Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process

Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process

Audio ADDA IP, 18 bits, Audio Codec, UMC 90nm SP process

Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process

Audio ADDA IP, 18/24 bits, 96KHz, UMC 0.13um HS/FSG process

Audio ADDA IP, 18/24 bits, 96KHz, UMC 0.13um HS/FSG process

Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process

Audio ADDA IP, 24 bits, 96KHz, UMC 40nm LP process

Audio ADDA IP, 24 bits, Audio Codec, UMC 40nm LP process

Audio ADDA IP, 24 bits, Audio Codec, UMC 40nm LP process

Audio ADDA IP, 24 bits, 96Ksps, UMC 40nm LP process

Audio ADDA IP, 6 bits, 44Msps, UMC 0.25um process

Analog & Mixed Signal->D/A Converter (DAC)->10-Bit DAC (35)

10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process

10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process

D/A Converter IP, 10 bits, 165Msps, UMC 90nm LL process

D/A Converter IP, 10 bits, 75MHz, UMC 65nm LL process

D/A Converter IP, 10 bits, 80Msps, UMC 0.13um SP/FSG process

D/A Converter IP, 10 bits, 150Msps, UMC 0.153um SP process

D/A Converter IP, 10 bits, 1MHz, UMC 0.153um MS process

D/A Converter IP, 10 bits, 44Msps, UMC 0.162um SP process

D/A Converter IP, 10 bits, 1MHz, UMC 0.18um G2 process

D/A Converter IP, 10 bits, 150Msps, UMC 55nm SP process

D/A Converter IP, 10 bits, RGB channels (3 - ch), 150Msps, current Output, UMC 90nm SP process

D/A Converter IP, 10 bits, 80MHz, UMC 90nm LL process

D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process

D/A Converter IP, 10 bits, 150Msps, UMC 55nm SP process

D/A Converter IP, 10 bits, 150Msps, UMC 55nm SP process

D/A Converter IP, 10 bits, 150Msps, UMC 55nm SP process

D/A Converter IP, 10 bits / 1MHz, Voltage output, UMC 0.11um HS/FSG process

D/A Converter IP, 10 bits, 1MHz, UMC 0.153um Logic process

D/A Converter IP, 10 bits, 1MHz, UMC 55nm SP process

D/A Converter IP, 10 bits, 1MHz, UMC 55nm SP process

D/A Converter IP, 10 bits / 250Msps, Current Output: / Differential end, UMC 0.11um HS/AE process

D/A Converter IP, 10 bits / 250Msps, Current Output, UMC 0.11um HS/AE process

D/A Converter IP, 10 bits / 150Msps, 3-channel, UMC 0.18um G2 process

D/A Converter IP, 10 bits / 150Msps, Current Output: / Differential end, UMC 0.13um HS/FSG process

D/A Converter IP, 10 bits / 150Msps, Current Output: / Differential end, UMC 0.13um LL/FSG process

D/A Converter IP, 10 bits / 150Msps, Current Output: / Single end, UMC 0.18um G2 process

D/A Converter IP, 10 bits / 250Msps, 3 channels / Current Output: / Single end, UMC 0.13um HS/FSG process

D/A Converter IP, 10 bits Delta-Sigma type, Duabl channel / Voltage Output: / Differential end, UMC 0.18um G2 process

D/A Converter IP, 10 bits, 150Msps, differential current Output, UMC 90nm SP process

D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process

D/A Converter IP, 10 bits / 1MHz, Voltage output, UMC 0.13um HS/FSG process

D/A Converter IP, 10 bits, 2.5Msps, HJTC 0.18um Logic process

D/A Converter IP, 10 bits, 250Msps, UMC 90nm SP process

Analog & Mixed Signal->D/A Converter (DAC)->12-Bit DAC (5)

12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process

12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process

D/A Converter IP, 12 bits, 80Msps, I-Q channels, UMC 55nm SP process

D/A Converter IP, 12 bits, 220Ksps, HJTC 0.18um eFlash process

D/A Converter IP, 12 bits, 50Ksps, HJTC 0.18um eFlash/G2 process

Analog & Mixed Signal->D/A Converter (DAC)->16-Bit DAC (3)

D/A Converter IP, 16 bits, 96Ksps, UMC 0.18um G2 process

D/A Converter IP, 16 bits, 96Ksps, UMC 0.25um Logic process

D/A Converter IP, 16/18/20/24 bits, 192Ksps, UMC 0.13um SP process

Analog & Mixed Signal->D/A Converter (DAC)->Other (12)

D/A Converter IP, Dual channel 10 bits current-steering type, 44Msps Differential current Output, UMC 0.18um G2 process

D/A Converter IP, 18 bits, Audio Codec, UMC 90nm SP process

D/A Converter IP, 8 bits, 250Msps, UMC 0.11um HS/AE process

D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/FSG process

D/A Converter IP, 6/8 bits, 44Msps, UMC 0.18um Logic/Mixed-Mode process

D/A Converter IP, 24 bits, 96KHz, UMC 0.11um HS/AE process

D/A Converter IP, 24 bits, 96KHz, UMC 0.11um HS/AE process

D/A Converter IP, 24 bits, 96KHz, UMC 0.11um HS/AE process

D/A Converter IP, 24 bits, 96KHz, UMC 55nm SP process

D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/AE process

D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/AE process

D/A Converter IP, UMC 40nm LP process

Analog & Mixed Signal->DC-DC Converter-> (19)

DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.2V/50mA, UMC 0.13um HS/FSG process

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/200mA, with soft-start, UMC 0.13um HS/FSG process

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process

DC-DC IP, Input: 3.3V, Output: 3.3V/300mA, UMC 0.153um MS process

DC-DC IP, Input: 2.5V / 3.3V, Output: 1.05V/250mA, UMC 0.11um HS/AE process

DC-DC IP, Input: 5V, Output: 3.3V/300mA, UMC 0.11um HS/AE process

DC-DC IP, Input: 0.95V - 1.5V, Output: 3V/100mA, UMC 0.11um HS/AE process

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 0.11um HS/AE process

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 40nm LP process

DC-DC IP, Input: 2.5V - 4.2V, Output: 3.3V/50uA, HJTC 0.18um eFlash/G2 process

DC-DC IP, Input: 3.3V, Output: 5V/50mA, HJTC 0.18um eFlash/G2 process

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process

DC-DC IP, Step-up PWM Regulator, Input: 3.0V - 3.6V, Output: 5V/100mA, with soft-start, UMC 0.13um HS/FSG process

Analog & Mixed Signal->DLL-> (56)

An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process .

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.

Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process

Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process

1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.

Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.

1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process

Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process

DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process

DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process

DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process

DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process

DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process

DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process

DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process

DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process

DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 0.11um HS/FSG process

DLL IP, Input: 18MHz - 45MHz, Output: 18 - 45MHz, UMC 90nm SP process

DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process

DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process

DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process

DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process

DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process

DLL (All Digital) IP, Input: 200MHz - 533MHz, Output: 200MHz - 533MHz, UMC 65nm LP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 40nm LP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm LP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm SP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz (Programmable output delay stepping with 1/64 clock period), UMC 55nm SP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 65nm LP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 65nm SP process

DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 90nm SP process

DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process

DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process

DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process

DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process

DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process

DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process

Analog & Mixed Signal->Oscillator-> (58)

RC Oscillator IP, Input: 1.62V - 1.98V, Output: 100KHz, HJTC 0.18um eFlash/G2 process

RC Oscillator IP, Input: 1.62V - 1.98V, Output: 40MHz, HJTC 0.18um eFlash/G2 process

RC Oscillator IP, Input: 1.62V - 1.98V, Output: 50MHz, HJTC 0.18um eFlash/G2 process

RC Oscillator IP, Output: 15MHz - 50MHz, UMC 0.25um process

RC Oscillator IP, Output: 25KHz/33MHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 30MHz, UMC 0.25um process

RC Oscillator IP, Output: 40MHz, UMC 0.18um G2 process

RC Oscillator IP, RC-Oscillator, Output: 32KHz, UMC 0.13um HS/AE process

Ring Oscillator IP, Output: 32KHz, UMC 0.11um eFlash/LL process

Ring Oscillator IP, Output: 8KHz, UMC 0.11um HS/AE process

Ring Oscillator IP, Output: 32KHz, UMC 55nm LP process

RC Oscillator IP, Output: 27.5MHz, UMC 0.35um Logic process

RC Oscillator IP, Output: 10KHz, UMC 0.35um Logic process

XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process

Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process

NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process.

Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process

internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process

NO External-R ,frequency 32.768MHz , Oscillator . Input 0.9V+/-10% ,1.2V+/-10% ; UMC 55nm ULP process.

Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process.

Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process

NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process.

Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process

Output frequency 32KHz. Input 0.9V-1.1V; UMC 55nm SP/RVT LowK Logic Process

Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

RC Oscillator IP, Output: 30KHz - 300KHz, UMC 0.25um Logic process

RC Oscillator IP, Output: 12KHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process

RC Oscillator IP, Output: 15MHz - 50MHz, UMC 0.13um HS/FSG process

RC Oscillator IP, Output: 40MHz, UMC 0.13um HS/FSG process

Ring Oscillator IP, Output: 12KHz, UMC 0.13um HS/FSG process

RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process

RC Oscillator IP, Output: 80MHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 50MHz, UMC 65nm SP process

RC Oscillator IP, Output: 12KHz, UMC 65nm LL process

RC Oscillator IP, Output: 10MHz, UMC 90nm LL process

RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process

RC Oscillator IP, Output: 40MHz, UMC 0.162um G2 process

RC Oscillator IP, Output: 50MHz, UMC 0.162um G2 process

RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 20MHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 25MHz / 33MHz, UMC 0.18um eFlash/G2 process

RC Oscillator IP, Output: 50MHz, UMC 0.18um G2 process

RC Oscillator IP, Output: 12KHz, UMC 65nm SP process

Ring Oscillator IP, Output: 12KHz, UMC 90nm Logic process

RC Oscillator IP, Output: 50MHz, UMC 90nm SP process

RC Oscillator IP, Output: 1.8432MHz, UMC 40nm LP process

RC Oscillator IP, Output: 10MHz, UMC 0.162um G2 process

RC Oscillator IP, Output: 25MHz / 33MHz, UMC 65nm LP process

RC Oscillator IP, Output: 48MHz, UMC 40nm LP process

RC Oscillator IP, Output: 50MHz, UMC 0.11um HS/FSG process

RC Oscillator IP, Output: 50MHz, UMC 0.162um eHV process

RC Oscillator IP, Output: 64KHz, UMC 0.13um HS/FSG process

RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/AE process

RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/AE process

RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process

Oscillator IP, Output: 5KHz, UMC 55nm SP process

Analog & Mixed Signal->Other-> (125)

Voltage Detector IP, 4 Levels, HJTC 0.18um eFlash/G2 process

Voltage Detector IP, 4 Levels, UMC 0.13um HS/FSG process

Voltage Detector IP, Vdet: 0.8V / 2.0V / 4.0V / 4.4V, UMC 0.18um G2 process

Voltage Detector IP, Vdet: 2.1V, UMC 0.25um process

Voltage Detector IP, Vdet: 2.4V, UMC 0.18um G2 process

Voltage Detector IP, Vdet: 2.8V, UMC 0.25um process

Band Gap IP, Input=1.0V-3.3V, VBG=0.75V with triming, Low power (1.8uW max, or 0.5uA@25C), UMC 55nm ULP process

Band Gap IP, VBG=1.23V, UMC 0.35um process

Voltage Detector IP, Vdet: 2.55V, UMC 0.35um process

Voltage Detector IP, Vdet: 3.3V, UMC 0.5um process

Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process

Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x005F_x005F_x000D_

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process

Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process

Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x000D_

Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process

Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process

Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process

5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process

8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process

Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process

Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process

Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process

Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process

Vrr=1.45V Vfr=1.35V, input 1.8V, Core type; Power On Reset; UMC 0.18um Logic GII process_x005F_x005F_x005F_x000D_

Vrr=0.8V,Vfr=0.65V,input VCC=1.2V, 1.2V Power On Reset; UMC 55nm e-flash Logic Process

Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process

Vrr=0.63V,Vfr=0.56V,input VCC=0.9V, 0.9V Power On Reset; UMC 28nm HPC Logic Process

3.3V Power On Reset, Vrr=1.90 without Vfr, UMC 40nm LP/RVT LowK Logic Process

3.3V RTC Power On Reset; UMC 55nm uLP/SST Logic Process

3.3V RTC Power On Reset; UMC 55nm uLP Logic Process

Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process

Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process

1.8V RTC Power-On-Reset, UMC 28nm HPC Process

Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process

Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process

Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process

Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process

2 Input Power Switch; UMC 55nm LP/RVT LowK Logic Process

3.3V to 1.1V / 600mA PWM, Switching Regulator, UMC 40nm LP/RVT LowK Logic Process

3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process

2.7V~3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process

3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process

3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process

3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process

3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library

3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

3.3V input , Programmable Output 1.8V/1.2V with 300mA driving capability; Linear Regulator; UMC 55nm SP/RVT LowK Logic Process

3.3v to 2.5v with 30mA driving capability without external capacitor (Cap-less), use trimming PADs; Linear Regulator; UMC 40nm LP/RVT LowK Logic process

3.3V to 1.8V with 50mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process

3.3V to 1.2V with 150mA driving capability, Istb=200uA; Linear Regulator; UMC 65nm LP/RVT LowK Logic Process

3.3V to 1.2V with 180mA driving capability; Linear Regulator; UMC 55nm eFlash LowK Logic process

3.3v to 1.1v/200mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic Process

3.3v to 1.1v/300mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic Process

3.3V to 1.1V with 30mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process

3.3V to 0.9V/150mA REG, Linear Regulator, UMC 28nm HPC Logic and Mixed-Mode Process

3.3v to 1.0v/100mA REG, Linear Regulator, UMC 55nm SP/RVT LowK Logic Process

3.3V to 1.2V with 220mA driving capability; Linear Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

3.3V to 1.2V with 220mA driving capability; Linear Regulator; UMC 0.11um eflash Process_x005F_x005F_x005F_x000D_

3.3V to 1.2V with 350mA driving capability; Linear Regulator; UMC 0.11£gm HS/FSG logic process_x005F_x005F_x005F_x000D_

3.3V to 1.2V with 150mA driving capability without external capacitor(Cap-less); use trimming ports (need e-Fuse IP); Linear Regulator; UMC 55nm eFlash LowK Logic Process

3.3v to 1.2v/150mA REG, Linear Regulator, UMC 55nm LP/RVT LowK Logic process

3.3V to 0.9V with 50mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process

3.3V to 1.2V with 150mA driving capability; Linear Regulator; UMC 0.13um LOGIC PROCESS

1.7V~3.6V to 1.0V with 600mA driving capability, Linear Regulator,UMC 55nm LP/RVT LowK Logic Process

5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process

5V to 3.3V/1.8V with 80mA/40mA driving capability, Linear Regulator; UMC 0.162um GII process._x005F_x005F_x005F_x000D_

3.3V to 1.8V with 10uA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process

3.3v to 1.2v/1ma with power switch function ,UMC 28nm HPC Logic process

3.3V to 0.9V with 2mA driving capability,Linear Regulator; UMC 28nm HPC Logic and Mixed-Mode process

3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process

3.3V to 1.2V/0.9V with 100mA driving capability;Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process

3.3V to 1.2V/0.9V with 100mA driving capability;Linear Regulator, UMC 55nm uLP/HVT Low-K Logic Process

3.3V to 2.0V with 288mA driving capability with external capacitor,use trimming ports (need e-Fuse IP); Linear Regulator; UMC 28nm Logic HPC Process

3.3V to 1.1V /50mA REG; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process_x005F_x005F_x005F_x000D_

3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 40nm Logic/Mixed-Mode Low Power Process

3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process

3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 0.11um HS/AE Logic Process

3.3V to 0.75*VCC33A with 5mA driving capability with external capacitor; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process

Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process

2 port Linear regulator for FXSATA168HD0A ; UMC 90nm SP/RVT LowK Logic Process

Source Low Dropout Linear Regulator for Cascade IO ; UMC 28nm HPC Process

Input 20M-66M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process

Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process

Voltage detector; UMC 55nm Logic SP/RVT Low-K Process

Power input 3.3v, 1-level voltage detector, UMC 40nm LP/RVT LowK Logic process

Power input 1.1v, 4-level voltage detector, UMC 40nm LP/HVT LowK Logic process

Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power supply monitoring system; UMC 55nm eFlash Process

4-level detector for USB-OTG applications, input 3.3V; UMC 0.11um eFlash Logic process_x005F_x005F_x005F_x000D_

4-Level Voltage Detector for USB-OTG ; UMC 55nm eflash LP/RVT Process

4-Level Voltage Detector for USB-OTG ; UMC 55nm 2.5V overdrive 3.3V device LP/HVT LowK Logic Process _x005F_x005F_x005F_x000D_

4-Level Voltage Detector for USB-OTG ; UMC 28nm HPC Process

2-sets voltage detector ; UMC 55nm Logic SP/RVT Low-K Process

2-sets voltage detector; UMC 55nm eflash LP/RVT Process

programmable voltage detector; umc55nm eflash

2-sets voltage detector; UMC 55 nm Logic LP/RVT Low-K Process

Power input 3.3v or 1.8v, 2-set voltage detector, UMC 28nm HPC Logic Process

programmable voltage detector; umc55nm eflash

2-sets voltage detector ;UMC 0.11nm Logic Mixed Mode AE Process

Power input 3.3V, Comparator ; UMC 55nm SST uLP/HVT Low-K Logic Process

Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library

TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.

Voltage Detector IP, UMC 0.25um Logic process

Voltage Detector IP, 3 Levels, UMC 0.18um G2 process

Voltage Detector IP, UMC 0.18um LL process

Voltage Detector IP, UMC 0.18um LL process

Voltage Detector IP, 4 Levels, UMC 0.13um LL/FSG process

Voltage Detector IP, 4 Levels, UMC 0.18um G2 process

Voltage Detector IP, 4 Levels, UMC 65nm LL process

Voltage Detector IP, 4 Levels, UMC 0.153um G2 process

Voltage Detector IP, VCC: 1.8V, Vdet=1.3V, UMC 0.18um G2 process

Voltage Detector IP, 4 Levels, UMC 55nm SP process

Voltage Detector IP, 4 Levels, UMC 65nm SP process

Voltage Detector IP, 4 Levels, UMC 90nm SP process

Voltage Detector IP, 4 Levels, UMC 90nm LL process

Voltage Detector IP, 4 Levels, UMC 0.11um HS/AE process

Voltage Detector IP, 4 Levels, UMC 40nm LP process

Voltage Detector IP, Vdet: 2.5V, UMC 0.11um HS/FSG process

PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process

Analog & Mixed Signal->PLL->Deskew PLL (1)

PLL (De-Skew) IP, Input: 15MHz - 110MHz, Output: 15MHz - 110MHz, UMC 0.13um HS/FSG process

Analog & Mixed Signal->PLL->General Purpose PLL (140)

PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process

Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process.

Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process

Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.

Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process

Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process

Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process

Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process

Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process

Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process

Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process

Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process

Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process

Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process

Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process

Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.

Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process

This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 50MHz - 100MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.13um HS/FSG process

PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 12.5MHz - 200MHz, UMC 0.18um LL process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 60MHz - 200MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 10MHz - 200MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 36MHz, Output: 500MHz - 1GHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 65nm SP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 65nm SP process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 500MHz, Output: 1000MHz - 1500MHz, UMC 65nm SP process

PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 12.5MHz - 300MHz, UMC 0.11um CIS process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 12.5MHz - 300MHz, UMC 0.11um CIS process

PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 66.66MHz, Output: 400MHz - 800MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 133MHz - 266MHz, Output: Output: 133MHz - 266MHz, 266MHz - 533MHz, 533MHz - 1066MHz, UMC 0.13um HS/FSG process

PLL IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 12.5MHz - 200MHz, UMC 0.13um LL/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 20MHz - 400MHz, UMC 0.13um LL/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 20MHz - 400MHz, UMC 0.13um LL/FSG process

PLL IP, Input: 32.768KHz, Output: 12MHz, UMC 0.153um G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.162um LL process

PLL (Frequency Synthesizer) IP, Input: 1MHz - 200MHz, Output: 12.5MHz - 200MHz, UMC 0.18um LL process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um eFlash/G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um LL process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um eFlash/G2 process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 800MHz/1000MHz, 533MHz/666MHz, 400MHz/500MHz, 266MHz/533MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 33MHz - 300MHz, Output: 1000MHz - 1500MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 33.33MHz - 100MHz, Output: 400MHz - 800MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 800MHz - 1600M, 400MHz - 800MHz and 200MHz - 400MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm SP process

PLL (Frequency Synthesizer) IP, Input: 1MHz - 5MHz, Output: 15MHz - 600MHz, UMC 65nm LL process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 33.33MHz, Output: 600MHz/800MHz, 400MHz/533MHz, 200MHz/266MHz, UMC 65nm SP process

PLL (Mini-PLL) IP, Input: 20MHz - 200MHz, Output: 31.5MHz - 500MHz, UMC 65nm SP process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 65nm LP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 65nm LL process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 90nm LL process

PLL (Frequency Synthesizer) IP, Input: 156.25MHz, Output: 625MHz, UMC 90nm SP process

PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 50MHz, Output: 667MHz - 1300MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 800MHz - 1600M, 400MHz - 800MHz and 200MHz - 400MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 20MHz - 300MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm LL process

PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 25/50MHz, Output: 400MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 33MHz/66MHz, Output: 1056MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 50MHz - 300MHz, UMC 90nm LL process

PLL IP, Input: 372M - 540MHz, Output: 5MHz - 420MHz, UMC 0.11um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process

PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process

PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um SP/FSG process

PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 96MHz - 180MHz, UMC 0.11um HS/AE process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 55nm LP process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 65nm LP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.11um HS/AE process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 28nm HPM process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process

PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 80MHz - 150MHz, Output: 80MHz - 150MHz, UMC 0.13um HS/FSG process

PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, HJTC 0.18um eFlash/G2 process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 10MHz, Output: 40MHz - 60MHz, HJTC 0.18um eFlash/G2 process

PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 120MHz / 540MHz, UMC 40nm LP process

PLL (Frequency Synthesizer) IP, Input: 1MHz - 200MHz, Output: 25MHz - 380MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 1MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 800MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 28nm HPM process

PLL (Frequency Synthesizer) IP, Input: 200MHz - 800MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 28nm HPM process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/AE process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HLP process

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 1GHz -1.5GHz, UMC 90nm SP process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process

PLL (Frequency Synthesizer) IP, Input: 25MHz - 27MHz, Output: 1050MHz - 1070MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 45KHz - 60KHz, Output: 81MHz - 132MHz, UMC 0.11um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 4MHz - 200MHz, Output: 20MHz - 400MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, , Output: 20MHz - 300MHz, UMC 0.25um process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 62.5MHz - 1000MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 62/5MHz - 1GHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 12.5MHz - 200MHz, UMC 0.13um LL process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um HS/FSG process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process

Analog & Mixed Signal->PLL->Spread Spectrum PLL (11)

PLL (Spread Spectrum) IP, UMC 40nm LP process

Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.

Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.

Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process.

PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process

PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process

PLL (All Digital, Spread Spectrum) IP, Input: clock range:10MHz - 1280MHz, Output: 15.625MHz - 2GHz, Spreading depth: -10%(max), Spreading Freq: 20KHz to 300KHz, UMC 0.11um HS/AE process

PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process

PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process

PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process

PLL (Spread Spectrum) IP, UMC 40nm LP process

Analog & Mixed Signal->Power Management-> (106)

Power on Reset IP, Input: 1.0V, UMC 90nm SP process

Power on Reset IP, Input: 1.1V, UMC 40nm LP process

Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um LL/FSG process

Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process

Power on Reset IP, Input: 1.2V, Vrr=0.8V, Vfr=0.65V, UMC 55nm LP process

Power on Reset IP, Input: 1.8V, HJTC 0.18um eFlash/G2 process

Power on Reset IP, Input: 1.8V, Output: 1.8432MHz, HJTC 0.18um eFlash/G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 2.5V/3.3V, HJTC 0.18um eFlash/G2 process

Power on Reset IP, Input: 2.5V, UMC 0.25um process

Power on Reset IP, Input: 2.5V, UMC 0.25um MS process

Power on Reset IP, Input: 3.3V, UMC 0.11um eFlash process

Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process

Power on Reset IP, UMC 0.11um eFlash process

Power on Reset IP, UMC 0.25um process

Power on Reset IP, UMC 0.25um process

Power on Reset IP, UMC 0.25um process

Power on Reset IP, UMC 0.25um MS process

Power Switch IP, 2 inputs, HJTC 0.18um eFlash/G2 process

Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process

Linear Regulator IP, Input: 1.0V - 3.6V, Output: 0.9V/20mA, Standby Current: 0.8uA, UMC 55nm ULP process

Linear Regulator IP, UMC 0.11um HS/AE process

Linear Regulator IP, UMC 0.18um G2 process

Linear Regulator IP, Output: 5V/50mA, UMC 0.35um process

Power on Reset IP, Input: 3.3V, UMC 0.35um process

Linear Regulator IP, Output: 5V/150mA, UMC 0.35um process

Linear Regulator IP, Output: 5V/70mA, UMC 0.35um Logic process

Power on Reset IP, Input: 5V, UMC 0.5um process

Power on Reset IP, Input: 3.3V, UMC 0.5um process

Power on Reset IP, Input: 3.3V, UMC 0.5um process

Power on Reset IP, Input: 1.0V/3.3V, UMC 40nm LP process

Power on Reset IP, Input: 1.8V, UMC 0.153um MS process

Power on Reset IP, Input: 2.5V, UMC 40nm LP process

Power on Reset IP, Input: 2.5V, UMC 40nm LP process

Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process

Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process

Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process

Power on Reset IP, UMC 0.162um eHV process

Linear Regulator IP, Input: 3.3V, Output: 1.1V/150mA, UMC 40nm LP process

Linear Regulator IP, Input: 3.3V, Output: 1.1V/200mA, UMC 40nm LP process

Linear Regulator IP, Input: 3.3V, Output: 2.5V/100mA, UMC 40nm LP process

Linear Regulator IP, Output: 1.1V/100mA, UMC 40nm LP process

Linear Regulator IP, Output: 1.1V/150mA, UMC 40nm LP process

Linear Regulator IP, Output: 1.2V/120mA, UMC 0.11um HS/FSG process

Linear Regulator IP, Output: 1.2V/120mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Output: 1.2V/150mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 1.2V/150mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 1.2V/150mA, UMC 55nm LP process

Linear Regulator IP, Output: 1.2V/400mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 1.2V/50mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 1.8V/100mA, UMC 0.11um HS/FSG process

Linear Regulator IP, Output: 1V/150mA, UMC 55nm SP process

Linear Regulator IP, Output: 1V/60mA, UMC 65nm SP process

Linear Regulator IP, Output: 2.5V/200mA, UMC 65nm LL process

Linear Regulator IP, Output: 2.5V/300mA, UMC 0.11um HS/FSG process

Linear Regulator IP, Output: 2.5V/50mA, UMC 40nm LP process

Linear Regulator IP, Output: 2.8V/20mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 2.8V/20mA, UMC 55nm SP process

Linear Regulator IP, Output: 3.3V/150mA, UMC 0.11um HS/FSG process

Linear Regulator IP, Output: 3.3V/300mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 3.3V/350mA, UMC 0.11um HS/AE process

Linear Regulator IP, Output: 3.3V/350mA, UMC 0.11um HS/FSG process

Band Gap IP, Input: 0.945V - 1.155V, VBG=0.8V, UMC 28nm HLP process

Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um G2 process

Band Gap IP, Input: 1.1V, VBG=0.48V, UMC 40nm LP process

Band Gap IP, Input: 1.1V, VBG=0.8V, UMC 40nm LP process

Band Gap IP, Input: 1.2V, VBG=0.4V, Operating current less than 70uA (125C), 1uA standby current, UMC 55nm LP process

Band Gap IP, Input: 1.8V - 3.6V, VBG=0.615V, UMC 0.162um eHV process

Band Gap IP, Input: 1V - 1.5V, VBG=0.615V, UMC 0.11um HS/AE process

Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.18um G2 process

Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 65nm LL process

Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 90nm SP process

Band Gap IP, Input: 2V - 3.6V, VBG=1.207V, UMC 0.11um HS/AE process

Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 40nm LP process

Band Gap IP, Input: 2V - 3.6V, VBG=1.2V, UMC 65nm LP process

Band Gap IP, Input: 3.3V, VBG=880.3 mV, UMC 55nm SP process

Band Gap IP, Input: 3V - 3.6V, VBG=1.22V, UMC 55nm SP process

Band Gap IP, Input: 1.0V ~ 2.1V, VBG=0.615V, UMC 0.18um G2 process

Band Gap IP, Input: 1.2V, VBG=0.8V, UMC 0.13um HS/FSG process

Band Gap IP, Input: 1.8V, VBG=0.615V, UMC 0.18um G2 process

Band Gap IP, Input: 2.25V - 2.75V, VBG=1.2V, UMC 55nm LP process

Band Gap IP, Input: 3.3V, VBG=1.23V, UMC 0.13um HS/FSG process

Band Gap IP, UMC 0.25um process

Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process

Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process

Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 150mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 process

Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 70mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 process

Linear Regulator IP, Input: 2.0V-4.0V, Output: 1.8V / 100mA, UMC 0.18um G2 process

Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process

Linear Regulator IP, Output: 3.3V/150mA, UMC 0.25um process

Linear Regulator IP, Output: 3.3V/250mA, UMC 0.25um process

Linear Regulator IP, Output: 3.3V/70mA, UMC 0.25um process

SATA II PHY IP, UMC 0.11um HS/FSG process

Linear Regulator IP, UMC 0.13um HS/FSG process

SATA II PHY IP, UMC 0.13um HS/FSG process

Linear Regulator IP, UMC 0.13um HS/FSG process

Linear Regulator IP, UMC 40nm LP process

Linear Regulator IP, UMC 40nm LP process

Linear Regulator IP, UMC 40nm LP process

Linear Regulator IP, UMC 90nm SP process

Linear Regulator IP, UMC 90nm SP process

Analog & Mixed Signal->Power Management->Other (27)

Power on Reset IP, Input: 1.5V, UMC 0.15um SP process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Vrr: 1.2V, Vfr: 1.1V, UMC 0.18um LL process

Power on Reset IP, Input: 1.2V, UMC 0.13um SP/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.2V, UMC 0.11um HS/AE process

Power on Reset IP, UMC 0.11um HS/FSG process

Power on Reset IP, Input: 3.3V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 2.5V - 3.3V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 3.3V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process

Power on Reset IP, Input: 1.2V, UMC 0.13um SP/FSG process

Power on Reset IP, Input: 1.8V, UMC 0.162um Logic process

Power on Reset IP, Vrr: 1.2V, Vfr: 1.0V, UMC 0.18um LL process

Power on Reset IP, Input: 1.8V, UMC 0.18um LL process

Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Power on Reset IP, Input: 1.8V, UMC 0.18um eFlash/G2 process

Power on Reset IP, Input: 1.0V, Vrr=0.67V, Vfr=0.62V, UMC 55nm SP process

Power on Reset IP, Input: 1.5V - 3.9V, UMC 55nm SP process

Power on Reset IP, Input: 1.0V, UMC 65nm SP process

Power on Reset IP, Vrr: 0.85V, Vfr: 0.75V, UMC 90nm LL process

Power on Reset IP, Input: 1.2V, UMC 90nm LL process

Power on Reset IP, Input: 3.3V, UMC 90nm SP process

Power on Reset IP, Input: 1.0V/3.3V, UMC 90nm SP process

Analog & Mixed Signal->Power Management->Regulator (25)

Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process

Linear Regulator IP, Output: 3.3V/240mA, UMC 0.18um LL process

Linear Regulator IP, Output: 3.3V/50mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Output: 3.3V/100mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Input: 3.3V, Output: 1.2V/1.0V/0.8V, 50mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Output: 1.2V/100mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Output: 3.3V/200mA, UMC 0.13um HS/FSG process

Linear Regulator IP, Output: 4.2V/1000mA, UMC 0.153um MS process

Linear Regulator IP, Output: 1.8V/150mA, UMC 0.153um MS process

Linear Regulator IP, Output: 1.8V/150mA, UMC 0.162um Logic process

Linear Regulator IP, Input: 3.3V, Output: 1.8V/150mA, UMC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 4.0-5.5V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 5.0V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um G2 process

Linear Regulator IP, Output: 3.3V/120mA, UMC 0.18um G2 process

Linear Regulator IP, Output: 2.5V/150mA, UMC 65nm SP process

Linear Regulator IP, Output: 1.2V/150mA, UMC 65nm LL process

Linear Regulator IP, Output: 1.2V/60mA, UMC 90nm LL process

Linear Regulator IP, Output: 1.2V/100mA, UMC 90nm SP process

Linear Regulator IP, Output: 1.8V/120mA, UMC 0.153um Logic process

Linear Regulator IP, HJTC 0.11um eFlash process

Linear Regulator IP, Input: 2.2 - 3.6V, Output: 1.8V/100mA, HJTC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 2.5V - 5.5V, Output: 1.8V/50mA, Iq=4uA, Idis=0.5uA, HJTC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 2.5V - 5.5V, Output: 3.3V/20mA, HJTC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 3.3V, Output: 1.8V/150mA, HJTC 0.18um eFlash/G2 process

Linear Regulator IP, Input: 5.0V, Output: 3.3V/250mA, 1.8V/70mA, HJTC 0.18um eFlash/G2 process

Analog & Mixed Signal->Power Management->Voltage Reference (19)

Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process

Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.15um SP process

Band Gap IP, Input: 1.0V - 1.2V, VBG=0.8V, UMC 0.13um LL/FSG process

Band Gap IP, Input: 1.2V - 3.3V, VBG=0.615V, UMC 0.18um G2 process

Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process

Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process

Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.13um HS/FSG process

Band Gap IP, Input: 1V - 1.5V, VBG=0.8V, UMC 0.11um HS/FSG process

Band Gap IP, Input: 1V - 1.5V, VBG=0.8V, UMC 0.11um HS/AE process

Band Gap IP, Input: 2.0V - 3.6V, VBG=1.22V, UMC 0.153um MS process

Band Gap IP, Input: 2.0V - 4.0V, VBG=1.23V, UMC 0.18um G2 process

Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 55nm SP process

Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 65nm SP process

Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 90nm SP process

Band Gap IP, Input: 0.9V - 1.1V, VBG=0.5V, UMC 90nm SP process

Band Gap IP, Input: 1.08V - 1.32V, VBG=0.6V, UMC 90nm LL process

Band Gap IP, Input: 1.2V - 1.98V, VBG=0.615V, UMC 0.153um Logic process

Band Gap IP, Input: 2.0V - 3.6V, VBG=1.21V, HJTC 0.18um eFlash/G2 process

Band Gap IP, Input: 2.5V - 5.5V, VBG=1.21V, HJTC 0.18um eFlash/G2 process

Analog & Mixed Signal->Temperature Sensor-> (1)

A 10bit 1ksps temperature to digital converter ; UMC 28nm HPC/RVT Logic and Mixed-mode Process

Foundation IP->Embedded Memories->Dual-Port SRAM (19)

Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process

Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process

Dual Port SRAM Compiler IP, UMC 0.11um HS/AE process

Dual Port SRAM Compiler IP, UMC 0.11um LL/AE process

Dual Port SRAM Compiler IP, UMC 0.11um HS/FSG process

Dual Port SRAM Compiler IP, UMC 0.153um MS process

Dual Port SRAM Compiler IP, UMC 0.18um MS process

Dual Port SRAM Compiler IP, UMC 55nm SP process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process

Dual Port SRAM Compiler IP, UMC 55nm SP process

Dual Port SRAM Compiler IP, UMC 65nm SP process

Dual Port SRAM Compiler IP, UMC 65nm LL process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process

Dual Port SRAM Compiler IP, UMC 65nm LL process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process

Dual Port SRAM Compiler IP, UMC 90nm LL process

Dual Port SRAM Compiler IP, UMC 90nm LL process

Foundation IP->Embedded Memories->Other (15)

ROM Compiler IP, UMC 0.15um SP process

ROM Compiler IP, UMC 0.18um LL process

ROM Compiler IP, UMC 90nm LL process

ROM Compiler IP, UMC 0.162um Logic process

ROM Compiler IP, UMC 65nm SP process

ROM Compiler IP, UMC 0.162um G2 process

ROM Compiler IP, UMC 0.11um LL/AE process

ROM Compiler IP, UMC 0.11um SP/AE process

ROM Compiler IP, UMC 0.13um HS/FSG process

ROM Compiler IP, UMC 0.13um CIS process

ROM Compiler IP, UMC 0.153um MS process

ROM Compiler IP, UMC 0.162um eHV process

ROM Compiler IP, UMC 0.25um Logic process

ROM Compiler IP, UMC 55nm SP process

ROM Compiler IP, UMC 65nm LL process

Foundation IP->Embedded Memories->RAM (158)

Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process

Dual Port SRAM Compiler IP, UMC 0.18um eFlash/G2 process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process

Dual Port SRAM Compiler IP, UMC 55nm LP process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process

Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process

Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process

Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process

Dual Port SRAM Compiler IP, UMC 0.11um LL process

Dual Port SRAM Compiler IP, UMC 0.11um SP process

Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process

Dual Port SRAM Compiler IP, UMC 0.13um LL process

Dual Port SRAM Compiler IP, UMC 0.18um G2 process

Dual Port SRAM Compiler IP, UMC 0.18um G2 process

Dual Port SRAM Compiler IP, UMC 28nm HLP process

Dual Port SRAM Compiler IP, UMC 28nm HLP process

Dual Port SRAM Compiler IP, UMC 28nm HLP process

Dual Port SRAM Compiler IP, UMC 55nm eHV process

Dual Port SRAM Compiler IP, UMC 55nm LP process

Dual Port SRAM Compiler IP, UMC 90nm SP process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um process

Single Port SRAM Compiler IP, UMC 0.35um SP process

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler

UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler

UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler

UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy

UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler

UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy

UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy

UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler

28nm HPM SP-SRAM with 1 column redundancy

28nm HPM SP-SRAM with 2 column redundancy

28nm HPM SP-SRAM with peri LVT

28nm HPM SP-SRAM with peri-LVT 1 column repair

28nm HPM SP-SRAM with peri LVT & 2 column repair

28nm HPM SP-SRAM with peri LVT row repair

28nm HPM SP-SRAM with peri LVT & row & 1 column repair

UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair

28nm HPM SH with Row redundancy

28nm HPM SP-SRAM with row and 1 column repair

28nm HPM SP-SRAM with Row and 2 Column Repair

UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler

UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler

UMC 40nm Low Power Process SP-SRAM with 213 bit cell

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT

UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.

UMC 40nm Low Power Process Single-Port SRAM for dual power rail

ULL Single Port SRAM with peri HVT, UMC 40nm LP process.

ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.

UMC 55nm eHV process;Single-Port SRAM compiler

UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy

UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.

UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.

UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.

UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.

UMC 55nm ULP/LowK process Single-Port SRAM

UMC 55nm ULP process , Single-Port SRAM with row repair and HVT

UMC 55nm ULP/LowK process Single-Port SRAM

UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler

UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler

UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler

UMC 28nm HPC process Dual Port SRAM compiler

UMC 28nm HPC process Dual Port SRAM with LVT

UMC 28nm HPC process Dual Port SRAM with row repair & LVT

UMC 28nm HPC process Dual Port SRAM with row reapir

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral

40LP High density dual port SRAM compiler with Vss booster feature

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy

UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 28nm HPC process Dual Port SRAM with Power gating

UMC 28nm HPC process PG-Dual Port SRAM with LVT

UMC 28nm HPC process PG Dual Port SRAM with LVT

UMC 28nm HPC Process dual port SRAM with power gating

UMC 40nm LP process standard synchronous high density TCAM memory compiler.

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler

UMC 28HPC process standard synchronous high density TCAM memory compiler

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler.

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.

HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM

UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler

UMC 90nm SPLVT ultra-high speed 1-port SRAM

55 SP Dual Port SRAM compiler with 1P4M metal option

UMC 55nm eFlash Single-Port SRAM memory compiler

UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier

UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler

UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy

UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler

55nm eFlash Dual-Port SRAM memory compiler with row redundancy

UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.

UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.

UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.

UMC 55nm LP process with PG Dual port SRAM compiler

UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell

UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT

40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell

UMC 40nm LP with power gating & peri-HVT 1PRF

UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail

UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail

UMC 40nm uLP process ULL Single-Port SRAM

UMC 40nm uLP process ULL One Port Register File memory compiler

UMC 28nm HPC process Dual Port SRAM compiler

UMC 28nm HPC process Dual Port SRAM compiler

UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.

UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.

UMC 28HPC process standard synchronous high density dual port SRAM memory compiler.

UMC 0.162um eFalsh/LL Single-Port SRAM memory compiler _x005F_x005F_x005F_x005F_x005F_x000D_

UMC 0.11um BCD process;Single-Port SRAM compiler

UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM

UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler.

UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler.

Foundation IP->Embedded Memories->ROM (62)

Single Port SRAM Compiler IP, UMC 0.11um EEPROM process

ROM Compiler IP, UMC 0.11um LL process

ROM Compiler IP, UMC 0.11um LL process

ROM Compiler IP, UMC 0.11um EEPROM process

ROM Compiler IP, UMC 0.11um CIS process

ROM Compiler IP, UMC 0.13um CIS process

ROM Compiler IP, UMC 0.18um LL process

ROM Compiler IP, UMC 40nm LP process

ROM Compiler IP, UMC 55nm eFlash process

ROM Compiler IP, UMC 55nm eHV process

ROM Compiler IP, UMC 55nm LP process

ROM Compiler IP, UMC 90nm CIS process

ROM Compiler IP, UMC 0.11um eFlash/HS process

ROM Compiler IP, UMC 0.11um HS/AE process

ROM Compiler IP, UMC 0.11um LL process

ROM Compiler IP, UMC 0.11um SP process

ROM Compiler IP, UMC 0.13um process

ROM Compiler IP, UMC 0.13um HS/FSG process

ROM Compiler IP, UMC 0.13um HS/FSG process

ROM Compiler IP, UMC 0.13um LL process

ROM Compiler IP, UMC 0.18um G2 process

ROM Compiler IP, UMC 0.18um G2 process

ROM Compiler IP, UMC 0.18um G2 process

ROM Compiler IP, UMC 0.18um LL process

ROM Compiler IP, UMC 0.25um process

ROM Compiler IP, UMC 0.25um process

ROM Compiler IP, UMC 0.25um process

ROM Compiler IP, UMC 0.25um process

ROM Compiler IP, UMC 0.25um process

ROM Compiler IP, UMC 0.25um SP process

ROM Compiler IP, UMC 28nm HLP process

ROM Compiler IP, UMC 28nm HLP process

ROM Compiler IP, UMC 40nm LP process

ROM Compiler IP, UMC 40nm LP process

ROM Compiler IP, UMC 40nm LP process

ROM Compiler IP, UMC 40nm LP process

ROM Compiler IP, UMC 55nm eFlash process

ROM Compiler IP, UMC 55nm LP process

ROM Compiler IP, UMC 90nm SP process

ROM Compiler IP, UMC 28nm HPC process

ROM Compiler IP, UMC 0.35um process

ROM Compiler IP, UMC 0.35um process

UMC 55nm Logic process standard synchronous Contact ROM memory compiler.

UMC 55nm Logic process standard synchronous Contact ROM memory compiler.

UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler.

UMC 55nm EFLASH Process Via ROM Memory complier

UMC 55nm ULP Low-K process HVT via1 ROM

UMC 55nm ULP/LowK Process via1 ROM compiler well bias

UMC 55nm ULP/LowK Process via ROM compiler for well bias

UMC 40nm ultra low power via1 ROM complier

UMC 40nm uLP process ULL Via1 ROM compiler

UMC 28nm HPC Process PG Via ROM Compiler

UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral

UMC 80nm LL/eHV Process synchronous Via ROM memory compiler

UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler.

UMC 55nm eFlash process process ULL ROM Memory Compiler

UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias

UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias

UMC 55nm ULP process ROM compiler with HVT peripheral

UMC 0.11um BCD High Voltage Process Synchronous Via1 Programmable ROM Compiler

HJTC 0.11um uLL/pFlash via1 ROM memory compiler.

Foundation IP->Embedded Memories->Register File (152)

Two Port Register File Compiler IP, UMC 0.11um SP/AE process

One Port Register File Compiler IP, UMC 0.11um HS/AE process

One Port Register File Compiler IP, UMC 0.11um HS/AE process

One Port Register File Compiler IP, UMC 0.11um LL/AE process

One Port Register File Compiler IP, UMC 0.11um LL process

One Port Register File Compiler IP, UMC 0.11um SP/AE process

One Port Register File Compiler IP, UMC 0.13um CIS process

One Port Register File Compiler IP, UMC 40nm LP process

One Port Register File Compiler IP, UMC 40nm LP process

One Port Register File Compiler IP, UMC 55nm eFlash process

One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process

One Port Register File Compiler IP, UMC 55nm SP process

One Port Register File Compiler IP, UMC 90nm LL process

Two Port Register File Compiler IP, UMC 0.11um LL process

Two Port Register File Compiler IP, UMC 0.11um HS/FSG process

Two Port Register File Compiler IP, UMC 40nm LP process

Two Port Register File Compiler IP, UMC 55nm LP process

Two Port Register File Compiler IP, UMC 90nm SP process

One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process

One Port Register File Compiler IP, HJTC 0.18um pFlash process

One Port Register File Compiler IP, UMC 0.11um HS/AE process

One Port Register File Compiler IP, UMC 0.11um HS/FSG process

One Port Register File Compiler IP, UMC 0.11um HS/FSG process

One Port Register File Compiler IP, UMC 0.11um LL process

One Port Register File Compiler IP, UMC 0.13um HS/FSG process

One Port Register File Compiler IP, UMC 0.13um HS/FSG process

One Port Register File Compiler IP, UMC 0.13um LL process

One Port Register File Compiler IP, UMC 0.13um SP process

One Port Register File Compiler IP, UMC 0.18um G2 process

One Port Register File Compiler IP, UMC 0.18um LL process

One Port Register File Compiler IP, UMC 0.25um process

One Port Register File Compiler IP, UMC 28nm HLP process

One Port Register File Compiler IP, UMC 28nm HLP process

One Port Register File Compiler IP, UMC 28nm HLP process

One Port Register File Compiler IP, UMC 28nm SP process

One Port Register File Compiler IP, UMC 40nm LP process

One Port Register File Compiler IP, UMC 40nm LP process

One Port Register File Compiler IP, UMC 55nm eFlash process

One Port Register File Compiler IP, UMC 90nm SP process

One Port Register File Compiler IP, UMC 90nm SP process

Two Port Register File Compiler IP, UMC 0.11um eFlash/HS process

Two Port Register File Compiler IP, UMC 0.11um HS/AE process

Two Port Register File Compiler IP, UMC 0.11um HS/FSG process

Two Port Register File Compiler IP, UMC 0.11um LL/FSG process

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process

Two Port Register File Compiler IP, UMC 0.13um HS/FSG process

Two Port Register File Compiler IP, UMC 0.13um LL process

Two Port Register File Compiler IP, UMC 0.18um G2 process

Two Port Register File Compiler IP, UMC 0.25um process

Two Port Register File Compiler IP, UMC 0.25um process

Two Port Register File Compiler IP, UMC 28nm HLP process

Two Port Register File Compiler IP, UMC 28nm HLP process

Two Port Register File Compiler IP, UMC 40nm LP process

Two Port Register File Compiler IP, UMC 40nm LP process

Two Port Register File Compiler IP, UMC 40nm LP process

Two Port Register File Compiler IP, UMC 55nm LP process

Two Port Register File Compiler IP, UMC 90nm SP process

One Port Register File Compiler IP, UMC 28nm HPC process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

Two Port Register File Compiler IP, UMC 0.35um process

UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler

UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT

UMC 28HPM UHS 1PRF

UMC 28nm HPM ultra high speed register compiler

UMC 40nm Low Power Process One Port Register File wit 213 cell

UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral

UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral

UMC 40nm Low Power Process One Port Register File with 213 cell

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.

UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.

UMC 55nm ULP-SST process PG One Port Register File for periphery HVT

UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler

UMC 40nm Low Power Process , Two Port Register File with dual power rail

UMC 55nm Standard Performance LowK Logic Process Two-Port Register File

UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler

UMC 0.18UM Mixed Mode/RF; Two Port Register File

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.

UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm EFLASH Process Two Port Register File

UMC 55nm EFLASH Process ULL One Port Register File

UMC 55nm eflash process , Two Port Register File memory compiler

UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_

55ULP-SST 1P-RF with forward biased and HVT periphery

55ULP-SST 1P-RF with forward biased and UHVT periphery

UMC 55nm ULP Low-K process One Port Register File for periphery HVT

UMC 55nm ULP process PG-One Port Register File for periphery HVT

UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature

UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT

UMC 28nm HPC process Two Port Register File

UMC 28nm HPC process 2PRF with Bank2

UMC 28nm HPC process Two Port Register File with Bank2

UMC 28nm HPC process Two Port Register File with peri LVT

UMC 28nm HPC process Two Port Register File with LVT and Bank2

UMC 28nm HPC process Two Port Register File with LVT and Bank4

UMC 28nm HPC process One Port Register File with LVT

UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler

UMC 28HPC 1PRF compiler with HVT peripheral

UMC 28HPC process 1PRF compiler with LVT peripheral

UMC 28nm HPC Logic process PG One Port Register File

UMC 28nm HPC Logic process PG-One Port Register File with HVT

UMC 28nm HPC Logic process PG One Port Register File with LVT

UMC 28nm HPC process PG Two Port Register File

UMC 28nm HPC process 2PRF with Bank2 & power gating

UMC 28nm HPC process PG-2PRF with Bank4

UMC 28nm HPC process PG Two Port Register File with peri-HVT

UMC 28nm HPC process 2PRF, HVT & Bank2

UMC 28nm HPC process PG-2PRF with HVT Bank4

UMC 28nm HPC process PG Two Port Register File with peri-LVT

UMC 28nm HPC process 2PRF with LVT and Bank 2

UMC 28nm HPC process PG-2PRF with LVT and Bank 2

28nm HPM 1PRF with peri -LVT

UMC 0.162um eFalsh/LL One Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_ memory compiler

110nm BCD process Synchronous High-Density Single-Port SRAM Compiler

HJTC 0.11um uLL/pFlash Single Port SRAM compiler

HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.

Ultra High Speed 1-Port Register File, 6TSRAM, Peri LVT/RVT

One Port Register File Compiler IP, UMC 0.15um SP process

One Port Register File Compiler IP, UMC 0.13um SP/FSG process

Two Port Register File Compiler IP, UMC 0.13um SP/FSG process

One Port Register File Compiler IP, UMC 90nm LL process

One Port Register File Compiler IP, UMC 0.11um CIS process

One Port Register File Compiler IP, UMC 65nm SP process

One Port Register File Compiler IP, UMC 0.11um LL/AE process

One Port Register File Compiler IP, UMC 0.11um SP/AE process

One Port Register File Compiler IP, UMC 0.13um CIS process

One Port Register File Compiler IP, UMC 0.153um MS process

One Port Register File Compiler IP, UMC 0.162um G2 process

One Port Register File Compiler IP, UMC 55nm SP process

One Port Register File Compiler IP, UMC 55nm SP process

One Port Register File Compiler IP, UMC 55nm SP process

One Port Register File Compiler IP, UMC 65nm LL process

Two Port Register File Compiler IP, UMC 0.11um LL/AE process

Two Port Register File Compiler IP, UMC 0.153um MS process

Two Port Register File Compiler IP, UMC 0.162um Logic process

Two Port Register File Compiler IP, UMC 55nm SP process

Two Port Register File Compiler IP, UMC 55nm SP process

Two Port Register File Compiler IP, UMC 65nm SP process

Two Port Register File Compiler IP, UMC 65nm LL process

Two Port Register File Compiler IP, UMC 90nm LL process

Foundation IP->Embedded Memories->Via ROM (1)

ROM Compiler IP, Via-1 type, UMC 0.13um SP/FSG process

Foundation IP->I/O Library->ESD Protection (11)

UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)

UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO

UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library

Foundation IP->I/O Library->General-Purpose I/O (GPIO) (171)

General Purpose IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 55nm SP process

General Purpose IO IP, 5V tolerance, UMC 0.11um SP/FSG process

General Purpose IO IP, UMC 0.11um SP/FSG process

General Purpose IO IP, 5V tolerance, UMC 0.11um HS/FSG process

General Purpose IO IP, UMC 0.11um HS/FSG process

General Purpose IO IP, 5V tolerance, UMC 0.11um LL/FSG process

General Purpose IO IP, UMC 0.11um LL/FSG process

General Purpose IO IP, 5V tolerance, UMC 0.13um LL/FSG process

General Purpose IO IP, UMC 0.13um LL/FSG process

General Purpose IO IP, UMC 0.13um HS/FSG process

General Purpose IO IP, 5V tolerance, UMC 0.13um CIS process

General Purpose IO IP, UMC 0.13um CIS process

General Purpose IO IP, 5V tolerance, UMC 0.13um LL/FSG process

General Purpose IO IP, UMC 0.13um LL/FSG process

General Purpose IO IP, UMC 0.13um HS/FSG process

General Purpose IO IP, UMC 0.13um HS/FSG process

General Purpose IO IP, 5V tolerance, UMC 0.153um LL process

General Purpose IO IP, UMC 0.153um LL process

General Purpose IO IP, 5V tolerance, UMC 0.15um SP process

General Purpose IO IP, UMC 0.15um SP process

General Purpose IO IP, UMC 0.18um eFlash/G2 process

General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, 5V input tolerance, UMC 0.18um CIS process

General Purpose IO IP, UMC 0.18um CIS process

General Purpose IO IP, UMC 0.18um CIS process

General Purpose IO IP, 5V input tolerance, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, 3.3V Operations, 5V input tolerance, UMC 0.18um Mixed-Mode process

General Purpose IO IP, 3.3V Operations, UMC 0.18um Mixed-Mode process

General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process

General Purpose IO IP, 1.8V BOAC EMMC I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process

General Purpose IO IP, UMC 28nm HPM process

General Purpose IO IP, UMC 55nm CIS process

General Purpose IO IP, UMC 55nm CIS process

General Purpose IO IP, 3.3V tolerance, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, 3.3V tolerance, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, UMC 90nm LL process

General Purpose IO IP, UMC 90nm Logic process

General Purpose IO IP, UMC 90nm SP process

General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process

General Purpose IO IP, UMC 90nm SP process

General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process

General Purpose IO IP, UMC 90nm SP process

General Purpose IO IP, True 3.3V, UMC 90nm SP process

General Purpose IO IP, UMC 90nm SP process

General Purpose IO IP, UMC 90nm SP process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 28nm HLP process

General Purpose IO IP, 3.3V with 5V tolerance, Power-On Control, BOAC (Bonding Over Active Circuit) support, UMC 40nm LP process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 40nm LP process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 55nm eFlash process

General Purpose IO IP, SD3.0 I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process

General Purpose IO IP, 5V tolerance, UMC 0.13um process

General Purpose IO IP, UMC 0.13um process

General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, 5V input tolerance, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um LL process

General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process

General Purpose IO IP, 5V tolerance, UMC 0.25um Logic process

General Purpose IO IP, UMC 0.25um Logic process

General Purpose IO IP, UMC 0.25um Logic process

General Purpose IO IP, 5V tolerance, UMC 0.25um Logic process

General Purpose IO IP, UMC 0.25um Logic process

General Purpose IO IP, UMC 0.25um Logic process

General Purpose IO IP, UMC 28nm HLP process

General Purpose IO IP, UMC 28nm HPC process

General Purpose IO IP, UMC 40nm LP process

General Purpose IO IP, 5V tolerance, UMC 55nm SP process

General Purpose Multi-Voltage IO IP, UMC 0.11um HS/AE process

General Purpose Multi-Voltage IO IP, UMC 28nm HLP process

General Purpose Multi-Voltage IO IP, With Power-on Control features, UMC 0.11um eFlash process

General Purpose IO IP, 5V tolerance, UMC 0.35um Logic process

General Purpose IO IP, UMC 0.35um Logic process

General Purpose IO IP, UMC 0.35um Logic process

General Purpose IO IP, 5V tolerance, UMC 0.35um Logic process

General Purpose IO IP, UMC 0.35um Logic process

General Purpose IO IP, UMC 0.35um Logic process

General Purpose IO IP, UMC 0.45um Logic process

General Purpose IO IP, UMC 0.45um Logic process

General Purpose IO IP, 5V tolerance, UMC 0.45um Logic process

General Purpose IO IP, UMC 0.45um Logic process

General Purpose IO IP, UMC 0.45um Logic process

General Purpose IO IP, UMC 0.5um Logic process

General Purpose IO IP, UMC 0.5um Logic process

General Purpose IO IP, 5V tolerance, UMC 0.5um Logic process

General Purpose IO IP, UMC 0.5um Logic process

General Purpose IO IP, UMC 0.5um Logic process

UMC 0.18um Logic GII Process true 3.3V RTC IO cell Library

UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library

UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library

UMC 0.162um eHV 3.3V/8.25V/16.5V Process Standard IO Library

UMC 0.11um HS/AL Logic Process True 3.3V Standard IO Cell Library

UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells

UMC 0.13um HS/FSG Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.

UMC 90nm LL/RVT process MULTI-VOLTAGE GENERIC I/O CELL USING 3.3V GOX52 IO

UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library

UMC 55nm SP-RVT 1P10M Logic Process 1.8V/3.3V multi-voltage BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library

UMC 40nm LP/RVT Logic Process 1.8V/3.0V multi-voltage BOAC eMMC I/O cell library

UMC 40nm LP/RVT Logic Process 1.8V/2.5V/3.3V multi-voltage generic POC BOAC I/O cell library

28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library

28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library

UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 0.25um LOGIC process standard Multi-Voltage IO

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um HS/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um LL/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

General Purpose IO IP, 1.8V Operations, UMC 0.18um eHV process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um Mixed-Mode/RF process

General Purpose IO IP, UMC 0.162um G2 process

General Purpose IO IP, 5V tolerance, UMC 0.162um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process

General Purpose IO IP, UMC 90nm LL process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um HS/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

General Purpose Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

General Purpose Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 0.13um LL/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um LL/FSG process

General Purpose Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process

General Purpose IO IP, 3.3V Operations, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), 5V input tolerance, UMC 0.18um LL process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um LL process

General Purpose Multi-Voltage IO IP, UMC 55nm SP process

General Purpose Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 65nm SP process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm LL process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm LL process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process

General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um HS/FSG process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.11um HS/AE process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um LL/FSG process

General Purpose Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.153um MS process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um LL process

General Purpose IO IP, UMC 0.18um G2 process

General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process

General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process

Foundation IP->I/O Library->High-speed (47)

LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um HS/FSG process

LVDS Transmitter IP, 8MHz - 100MHz, 4 channels, UMC 0.18um G2 process

LVDS Transmitter IP, 1200Mbps, UMC 55nm SP process

LVDS Transmitter IP, 700Mbps, UMC 0.13um SP/FSG process

LVDS Transmitter IP, 700Mbps, UMC 55nm SP process

LVDS Transmitter IP, 700Mbps, UMC 90nm SP process

LVDS Transmitter IP, 85MHz, UMC 55nm SP process

LVDS Receiver IP, 500Mbps, UMC 55nm LP process

LVDS Tx IO IP, 1.25GHz, UMC 90nm SP process

LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process

LVDS Tx IO IP, UMC 0.35um Logic process

10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process

Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process

LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad.

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process

3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process

UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process

8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process

3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process

LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip

The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process

The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process

The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process

The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process

2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process

3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process

3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces

0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )

LVDS Transmitter 700Mbps; UMC 28nm HPC Process

3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process

2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.

100MHz single-ended to differential clock buffer for UMC 40nm LP.

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process

1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V

Foundation IP->I/O Library->LVDS (15)

LVDS Rx IO IP, UMC 0.18um G2 process

LVDS Rx IO IP, UMC 90nm SP process

LVDS Transmitter IP, Tx IO, UMC 55nm SP process

LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process

LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process

LVDS Tx IO IP, UMC 90nm SP process

LVDS Transmitter IP, 700Mbps, UMC 90nm SP process

LVDS Receiver IP, UMC 90nm SP process

LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process

LVDS Rx IO IP, 500Mbps, UMC 90nm LL process

LVDS Rx IO IP, UMC 0.18um Logic process

LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process

LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process

LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process

LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process

Foundation IP->I/O Library->Memory Interfaces (2)

Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process

Foundation IP->I/O Library->Special (193)

Specialty Analog ESD IO IP, UMC 0.18um LL process

Specialty Analog ESD IO IP, UMC 0.18um LL process

Specialty Analog ESD IO IP, 0.9V Operations, UMC 28nm HPM process

Specialty Analog ESD IO IP, 1.1V Operations, UMC 40nm LP process

Specialty Analog ESD IO IP, 1.8V Operations, UMC 28nm HPM process

Specialty Analog ESD IO IP, 3.3V, UMC 40nm LP process

Specialty DDR IO IP, DDR2/DDR1/MDDR, UMC 0.11um HS/AE process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 40nm LP process

Specialty OSC IO IP, 1MHz to 66MHz, UMC 55nm LP process

Specialty OSC IO IP, UMC 90nm LL process

Specialty OSC IO IP, UMC 90nm LL process

Specialty OSC IO IP, UMC 90nm SP process

Specialty OSC IO IP, 1MHz to 66MHz, UMC 90nm SP process

Specialty PCI IO IP, UMC 90nm SP process

Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process

Specialty SSTL IO IP, UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, UMC 28nm HLP process

Specialty Analog ESD IO IP, UMC 40nm LP process

Specialty Analog ESD IO IP, UMC 40nm LP process

Specialty Analog ESD IO IP, UMC 55nm CIS process

Specialty I2C IO IP, UMC 40nm LP process

Specialty OSC IO IP, 1MHz to 66MHz, UMC 55nm SP process

Specialty OSC IO IP, HJTC 0.18um eFlash/G2 process

Specialty OSC IO IP, HJTC 0.18um eFlash/G2 process

Specialty OSC IO IP, UMC 0.11um HS/AE process

Specialty OSC IO IP, UMC 0.25um Logic process

Specialty OSC IO IP, UMC 28nm HLP process

Specialty OSC IO IP, UMC 40nm LP process

Specialty OSC IO IP, UMC 40nm LP process

Specialty PCI IO IP, 5V tolerance, UMC 0.35um Logic process

Specialty OSC IO IP, UMC 0.35um Logic process

Specialty OSC IO IP, UMC 0.35um Logic process

Specialty OSC IO IP, UMC 0.35um Logic process

Specialty PCI IO IP, 5V tolerance, UMC 0.35um Logic process

Specialty OSC IO IP, UMC 0.35um Logic process

Specialty OSC IO IP, UMC 0.35um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, 5V tolerance, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.45um Logic process

Specialty PCI IO IP, UMC 0.5um Logic process

Specialty PCI IO IP, UMC 0.5um Logic process

Specialty PCI IO IP, UMC 0.5um Logic process

Specialty PCI IO IP, UMC 0.5um Logic process

UMC 0.5um LOGIC process Low Voltage Gate Array true 5.0V Oscillator IO cells

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad

UMC 55nm SP/RVT LowK Logic Process True 3.3V Low Frequency OSC IO Cell Library

UMC 55nm e-flash Logic Process OSC High IO Library

UMC 55nm e-flash Logic Process OSC High IO Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

Faraday 1.8V crystal oscillator I/O Cell Library ; UMC 14nm LOGIC_MIXED-FF+ Process

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library

UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process High-Freq0. OSC BOAC I/O.

UMC 0.11um SP/AE (AL Advanced Enhancement) Logic Process High-Freq. OSC BOAC I/O.

UMC 0.35um embedded HV Process 3.3V Crystal IO library

UMC 0.35um embedded HV Process 3.3V Crystal Low Frequency IO library

UMC 0.13um LL process PCI I/O cells. These I/O cells are designed to meet PCI-33 and PCI-66 applications. This IP is branched from 'FSC0L_D_50VT_PCI3366_IO'

UMC 90nm Logic/Mixed Mode SP(RVT) Low-K process;True 3.3V PECL IO Library.

UMC 90nm SP RVT process SSTL18 IO cell library

UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library

Specialty PCI IO IP, 5V tolerance, UMC 0.25um Logic process

Specialty SSTL IO IP, UMC 0.25um Logic process

Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

Specialty PCI IO IP, 5V tolerance, UMC 0.15um SP process

Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.15um SP process

Specialty OSC IO IP, UMC 0.15um SP process

Specialty PCI IO IP, UMC 0.15um SP process

Specialty SSTL IO IP, UMC 0.18um G2 process

Specialty PECL IO IP, UMC 0.18um G2 process

Specialty PCI IO IP, UMC 0.18um G2 process

Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, UMC 0.13um SP/FSG process

Specialty Analog ESD IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um LL/AE process

Specialty Analog ESD IO IP, UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, UMC 0.13um HS/FSG process

Specialty PECL IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um SP/FSG process

Specialty OSC IO IP, UMC 0.13um HS/FSG process

Specialty PCI IO IP, UMC 0.13um HS/FSG process

Specialty SSTL IO IP, UMC 0.13um HS/FSG process

Specialty SSTL IO IP, UMC 0.13um LL/FSG process

Specialty Analog ESD IO IP, UMC 0.13um LL/FSG process

Specialty Analog ESD IO IP, UMC 0.13um LL/FSG process

Specialty OSC IO IP, UMC 0.13um LL/FSG process

Specialty OSC IO IP, UMC 0.13um LL/FSG process

Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.15um SP process

Specialty OSC IO IP, UMC 0.15um SP process

Specialty PECL IO IP, UMC 0.15um G2 process

Specialty Analog ESD IO IP, 1.5V Operations, UMC 0.15um SP process

Specialty Analog ESD IO IP, 3.3V, UMC 0.15um SP process

Specialty OSC IO IP, 1.8V Operations, UMC 0.18um G2 process

Specialty OSC IO IP, Freq: 32KHz - 1MHz, UMC 0.18um G2 process

Specialty SSTL IO IP, UMC 0.18um Logic process

Specialty SSTL IO IP, UMC 0.18um Logic process

Specialty OSC IO IP, UMC 0.18um LL process

Specialty OSC IO IP, UMC 0.18um LL process

Specialty Analog ESD IO IP, 1.8V/3.3V Operations, UMC 0.18um G2 process

Specialty Analog ESD IO IP, UMC 0.18um G2 process

Specialty Analog ESD IO IP, UMC 0.18um LL process

Specialty Analog ESD IO IP, UMC 0.18um LL process

Specialty OSC IO IP, UMC 0.25um Logic process

Specialty OSC IO IP, UMC 0.25um Logic process

Specialty OSC IO IP, UMC 0.25um Logic process

Specialty OSC IO IP, UMC 0.25um Logic process

Specialty Analog ESD IO IP, UMC 0.25um Logic process

Specialty Analog ESD IO IP, UMC 0.11um HS/FSG process

Specialty OSC IO IP, UMC 0.11um HS/FSG process

Specialty OSC IO IP, UMC 0.162um G2 process

Specialty Analog ESD IO IP, UMC 0.11um HS/FSG process

Specialty OSC IO IP, UMC 0.11um SP/FSG process

Specialty OSC IO IP, UMC 0.11um SP/FSG process

Specialty OSC IO IP, UMC 0.11um HS/FSG process

Specialty Analog ESD IO IP, UMC 0.11um LL/FSG process

Specialty OSC IO IP, UMC 0.11um LL/FSG process

Specialty OSC IO IP, UMC 0.11um LL/FSG process

Specialty PCI IO IP, 5V tolerance, UMC 0.18um G2 process

Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty PECL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 0.18um G2 process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty PECL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process

Specialty SSTL IO IP, UMC 0.18um G2 process

Specialty SSTL IO IP, UMC 0.18um G2 process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process

Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 65nm SP process

Specialty OSC IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm LL process

Specialty SSTL IO IP, UMC 0.13um HS/FSG process

Specialty SSTL IO IP, UMC 0.13um MS process

Specialty SSTL IO IP, UMC 0.15um SP process

Specialty SSTL IO IP, UMC 0.18um G2 process

Specialty SSTL IO IP, UMC 0.18um G2 process

Specialty SSTL IO IP, UMC 0.25um Logic process

Specialty SSTL IO IP, UMC 0.13um HS/FSG process

Specialty PCI IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um HS/FSG process

Specialty OSC IO IP, UMC 0.13um HS/FSG process

Specialty Analog ESD IO IP, UMC 0.153um LL process

Specialty OSC IO IP, UMC 0.153um MS process

Specialty OSC IO IP, UMC 0.153um MS process

Specialty Analog ESD IO IP, UMC 0.153um LL process

Specialty OSC IO IP, UMC 0.153um MS process

Specialty Analog ESD IO IP, UMC 0.153um LL process

Specialty PCI IO IP, 5V tolerance, UMC 0.18um G2 process

Specialty Analog ESD IO IP, UMC 0.18um G2 process

Specialty OSC IO IP, UMC 0.18um G2 process

Specialty Analog ESD IO IP, UMC 0.18um G2 process

Specialty PECL IO IP, UMC 0.18um G2 process

Specialty PCI IO IP, UMC 0.18um G2 process

Specialty OSC IO IP, UMC 0.18um eFlash/G2 process

Specialty OSC IO IP, UMC 0.18um eFlash/G2 process

Specialty OSC IO IP, UMC 0.18um LL process

Specialty OSC IO IP, UMC 0.18um LL process

Specialty PCI IO IP, UMC 0.18um G2 process

Specialty Analog ESD IO IP, UMC 0.25um Logic process

Specialty PCI IO IP, UMC 65nm SP process

Specialty Analog ESD IO IP, UMC 90nm SP process

Specialty Analog ESD IO IP, UMC 90nm SP process

Specialty OSC IO IP, UMC 90nm SP process

Specialty Analog ESD IO IP, UMC 90nm SP process

Specialty Analog ESD IO IP, UMC 90nm SP process

Specialty Analog ESD IO IP, UMC 90nm LL process

Specialty Analog ESD IO IP, UMC 90nm LL process

Specialty Analog ESD IO IP, UMC 90nm LL process

Foundation IP->Standard cell-> (493)

Standard Cell (ECO) Library IP, 6 tracks, UMC 0.11um eFlash process

Standard Cell (ECO) Library IP, UMC 0.11um SP/FSG process

Standard Cell (ECO) Library IP, UMC 0.13um eHV process

Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, HVT, 9 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, LVT, 9 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, HVT, 8 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, LVT, 8 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, RVT, 8 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 55nm LP process

Standard Cell (ECO) Library IP, RVT, UMC 55nm SP process

Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 55nm SP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 55nm SP process

Standard Cell (Generic) Library IP, 8 tracks, UMC 90nm CIS process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um eFlash process

Standard Cell (Generic) Library IP, RTC Cell, UMC 0.11um eFlash process

Standard Cell (Generic) Library IP, RVT, UMC 40nm LP process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um eFlash/HS process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um eFlash/LL process

Standard Cell (Generic) Library IP, UMC 0.13um CIS process

Standard Cell (Generic) Library IP, UMC 0.18um CIS process

Standard Cell (Generic) Library IP, UMC 0.18um CIS process

Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell (Generic) Library IP, HVT, 8 tracks, UMC 55nm LP process

Standard Cell (Generic) Library IP, LVT, 8 tracks, UMC 55nm LP process

Standard Cell (Generic) Library IP, RVT, 8 tracks, UMC 55nm LP process

Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.135um eHV process

Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.13um eHV process

Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.162um eHV process

Standard Cell (High Voltage) Library IP, UMC 0.13um HS/FSG process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um G2 process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um eFlash/HS process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 40nm LP process

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 40nm LP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 40nm LP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm LP process

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 55nm LP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm LP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process

Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 55nm LP process

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process

Standard Cell PowerSlash(TM) Library IP, 7 tracks, UMC 0.11um HS/FSG process

Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process

Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/LL process

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process

Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HPC process

Standard Cell (ECO) Library IP, HVT, 9 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, HVT, UMC 40nm LP process

Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HPC process

Standard Cell (ECO) Library IP, LVT, 9 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, LVT, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HPC process

Standard Cell (ECO) Library IP, RVT, UMC 40nm LP process

Standard Cell (ECO) Library IP, RVT, UMC 65nm SP process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um eFlash/LL process

Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, 10-track, HVT, UMC 90nm SP process

Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, LVT, UMC 40nm LP process

Standard Cell (Generic) Library IP, RTC Cell, HJTC 0.18um eFlash/G2 process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process

Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 28nm HLP process

Standard Cell (Generic) Library IP, RVT, UMC 40nm LP process

Standard Cell (Generic) Library IP, RVT, UMC 90nm LL process

Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process

Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process

Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process

Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process

Standard Cell (Generic) Library IP, UMC 0.13um LL process

Standard Cell (Generic) Library IP, UMC 0.13um LL process

Standard Cell (Generic) Library IP, UMC 0.13um LL process

Standard Cell (Generic) Library IP, UMC 0.13um LL process

Standard Cell (Generic) Library IP, UMC 0.13um LL/FSG process

Standard Cell (Generic) Library IP, UMC 0.13um SP process

Standard Cell (Generic) Library IP, UMC 0.13um SP process

Standard Cell (Generic) Library IP, UMC 0.15um SP process

Standard Cell (Generic) Library IP, UMC 0.18um G2 process

Standard Cell (Generic) Library IP, UMC 0.18um G2 process

Standard Cell (Generic) Library IP, UMC 0.18um LL process

Standard Cell (Generic) Library IP, UMC 0.18um LL process

Standard Cell (Generic) Library IP, UMC 0.18um MS process

Standard Cell (Generic) Library IP, UMC 0.25um process

Standard Cell (Generic) Library IP, UMC 0.25um process

Standard Cell (Generic) Library IP, UMC 0.25um process

Standard Cell (Generic) Library IP, UMC 0.25um process

Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process

Standard Cell (MiniLib) Library IP, 7 tracks, HJTC 0.18um eFlash/G2 process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process

Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process

Standard Cell (RTC) Library IP, UMC 55nm ULP process

Standard Cell (Generic) Library IP, UMC 0.13um process

Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.3um HV process

Standard Cell (Generic) Library IP, UMC 0.35um HV/CDMOS process

Standard Cell (Generic) Library IP, UMC 0.35um Logic process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.35um Logic process

Standard Cell (Generic) Library IP, UMC 0.45um process

Standard Cell (Generic) Library IP, UMC 0.45um process

Standard Cell (Generic) Library IP, UMC 0.5um process

Standard Cell (Generic) Library IP, UMC 0.5um process

UMC 55nm eFlash/HVT Logic Process High Speed 12-track ECO_M1 cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)

UMC 28nm HPM/HVT Logic Process 12-track eco_m1_core library (C35)

UMC 28nm HPM/LVT Logic Process 12-track eco_m1_core library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)

UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library

UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library

UMC 0.13um HS/FSG Logic Process metal2-start programming gate array cell library for FSC0H_J (ECO_M2)

UMC 0.13um LL/FSG Logic Process Metal1 Start ECO core cell library

UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library

UMC 55nm eFlash/HVT Logic Process 7-track ECO_M1 cell library

UMC 55nm eFlash/LVT Logic Process 7-track ECO_M1 Generic cell library

UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library

UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPM/HVT Logic Process 9-track Standard ECO_M1 cell library (C35)

UMC 28nm HPM/HVT Logic Process 9-track Standard cell ECO_M1 CORE library (C38)

UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C31)

UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C35)

UMC 28nm HPM/RVT Logic Process 9-track ECO_M1 core cell library (C31)

UMC 28nm HPM/RVT Process 9-track ECO core cells Library(35nm)

UMC 28nm HPM/RVT Logic Process 9-track Standard ECO_M1 CORE cell library (C38)

UMC 0.18um GII Logic Process 3.3V core cell library

UMC 55nm eFlash/HVT Logic Process High Speed 12-track Genernic Core cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Cell library (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C40)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C30)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40)

UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LMINUS (C30)

UMC 28nm HPM/HVT Logic Process 12-track generic_core library (C35)

UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LPLUS (C38)

UMC 28nm HPM/LVT Logic Process 12-track generic cell library with LMINUS (C-31)

UMC 28nm HPM/LVT Logic Process 12-track generic cell library

UMC 28nm HPM/LVT Logic Process 12-track generic_core library with LPKUS (C38)

UMC 28nm HPM/RVT Logic Process 12-track generic_core library with LMINUS (C31)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 1.8V device RTC Core Library

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm eFlash/HVT Logic Process 7-track Genernic Core cell library

UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library

UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library

UMC 40nm uLP/HVT Logic Process SYNS-like 7T GENERIC CORE Cell Library

UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library

UMC 40nm uLP/RVT Logic Process SYNS-like 7T GENERIC CORE Cell Library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 HVT)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track generic core cell library

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 HVT)

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)

UMC 80nm HV Process High Density Standard Cell Library

UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track Genernic Core cell Library

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias

UMC 55nm LP/RVT LowK Logic Process 2.5VOD3.3V device RTC Core Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm LP/RVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm uLP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm uLP/LVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm uLP/RVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPM/HVT Logic Process std. generic core cell library (C31)

UMC 28nm HPM/HVT Logic Process 9-track Standard Generic Core cell library (C35)

UMC 28nm HPM/HVT Logic Process 9-track Standard generic core cell library (C38)

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic Core cell library (C31)

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic core cell library (C35)

UMC 28nm HPM/LVT Logic Process 9-track generic core cell library (C38)

UMC 28nm HPM/RVT Logic Process 9-track Standard Generic Core cell library (C31)

UMC 28nm HPM/RVT 9-track generic core cells(35nm)

UMC 28nm HPM/RVT Logic Process 9-track Standard generic core cell library (C38)

UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit

UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit

UMC 55nm eFlash/HVT Logic Process High Speed 12-track PowerSlash Kit cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)

UMC 28nm HPM/HVT Logic Process 12-track powerslash_core library (C35)

UMC 28nm HPM/LVT Logic Process 12-track powerslash_core library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)

UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)

UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)

UMC 0.18um Generic process MPCA core cell library

UMC 90nm LL/RVT MPCA core cell library

UMC 65nm SP/RVT Logic Process MPCA cell library

UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming

UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4

UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming

Fujitsu 90nm LL-UHS process MPCA M345 core cell library

Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]

UMC 55nm LP/LVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm LP/RVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 0.11um CIS Process cell library

UMC 0.11um AL/LL Logic Process miniLib standard cell library

HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.15um SP process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.13um SP/FSG process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.13um CIS process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process

Standard Cell (Generic) Library IP, 10-track, LVT, UMC 90nm SP process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um SP/FSG process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um HS/FSG process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um LL/FSG process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um LL process

Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 90nm LL process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um LL/FSG process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um HS/AE process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um HS/AE process

Standard Cell (Generic) Library IP, 10 tracks, UMC 0.11um HS/FSG process

Standard Cell (ECO) Library IP, UMC 0.11um HS/FSG process

Standard Cell (Generic) Library IP, 6 tracks, UMC 0.11um HS/FSG process

Standard Cell (Generic) Library IP, UMC 0.11um LL/AE process

Standard Cell (ECO) Library IP, UMC 0.11um SP/FSG process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um LL/AE process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um SP process

Standard Cell (Generic) Library IP, 8 tracks, UMC 0.13um SP/FSG process

Standard Cell (ECO) Library IP, UMC 0.13um HS/FSG process

Standard Cell (ECO) Library IP, UMC 0.13um LL/FSG process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.153um LL process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.18um eFlash/G2 process

Standard Cell (Generic) Library IP, 9 tracks, UMC 0.18um HV process

Standard Cell (Generic) Library IP, HVT, 8 tracks, UMC 65nm SP process

Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 65nm SP process

Standard Cell (ECO) Library IP, RVT, UMC 90nm SP process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 90nm SP process

Standard Cell (Generic) Library IP, RVT, 10 tracks, UMC 90nm SP process

Standard Cell (Generic) Library IP, RVT, UMC 90nm SP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 90nm SP process

Standard Cell (Generic) Library IP, HVT, 10 tracks, UMC 90nm SP process

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 90nm LL process

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 90nm LL process

Standard Cell (Generic) Library IP, RVT, RTC Cell, UMC 90nm LL process

Standard Cell (Generic) Library IP, LVT, 10 tracks, UMC 90nm SP process

Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 90nm LL process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um HS/AE process

Standard Cell (MiniLib) Library IP, UMC 0.11um SP/AE process

Standard Cell (MiniLib) Library IP, UMC 0.11um HS/AE process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um SP/FSG process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um HS/FSG process

Standard Cell (ECO) Library IP, UMC 0.11um HS/FSG process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um LL/FSG process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um HS/FSG process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um SP/FSG process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um SP/FSG process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um HS/FSG process

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.153um MS process

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.162um G2 process

Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 55nm SP process

Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 55nm SP process

Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm SP process

Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 65nm LL process

Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm LL process

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm SP process

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 65nm SP process

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 65nm LP process

General Purpose Processor IP->DSP Core->16-Bit (2)

16-bit digital signal processor soft core._x005F_x005F_x005F_x005F_x005F_x000D_

16-bit digital signal processor soft core.

General Purpose Processor IP->DSP Core->24-Bit (1)

24-bit digital signal processor soft core.

General Purpose Processor IP->Microcontroller-> (1)

8-bit micro-controller high speed 4clk/machine cycle architecture256 bytes of on-chip Data RAM,Three 16-bit timer/countersTwo 16-bit dptr

General Purpose Processor IP->Microcontroller->8-Bit Microcontroller (3)

FT8032 0.25um shrink to 0.22um

High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counter, and two 16-bit dptr; UMC 0.18um logic GII process.

High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.

General Purpose Processor IP->Processor Cores->32-Bit Microprocessor (1)

Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU

Graphic - Peripheral IP->Interrupt Controller-> (1)

Interrupt controller with APB interface

Graphic - Peripheral IP->Other-> (9)

ADC controller for Faraday internal use.

Cipher coprocess for encryption/decryption of DES/Triple-DES/AES algorithm.

AHB-Lite Slave wrapper, it is a protocol converter from AHB to AHB lite.

AHB-to-APB simple bridge.

Intelligent Energy Controller for voltage and frequency scaling.

Timer with APB interface and PWM output function

SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00

The FTWDT011 is an independent watchdog peripheral which offers a clocked by a dedicated clock through the external port and thus stays active event if the main clock fails. It can serve to detect and resolve malfunctions due to software failure, and to t

Touch Controller IP, Soft IP

Graphic - Peripheral IP->Receiver/Transmitter-> (1)

UART/IrDA controller with APB interface

Graphic - Peripheral IP->Timer/Watchdog-> (4)

Watchdog IP, 66MHz APB clock rate, 32 - bit down counter, Soft IP

Real time clock with APB interface

Timer with APB interface

Timer IP, Real Time Clock, Clock cource: 100MHz APB bus or 32768Hz input, Soft IP

Interface Controller - PHY IP->AMBA AHB / APB/ AXI->AMBA AHB / APB (16)

APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP

Direct memory access controller with AHB interface

APB Fundamental Peripheral IP, I2C controller, Soft IP

AHB system Peripheral IP, IDE Host controller, Soft IP

APB Fundamental Peripheral IP, IO controller, Soft IP

APB Fundamental Peripheral IP, Keyboard/Mouse controller, Configurable keypad matrix from 4x4 to 8x16, Soft IP

AHB system Peripheral IP, SDRAM controller, Soft IP

AHB system Peripheral IP, SRAM controller, Soft IP

AHB system Peripheral IP, AHB Arbiter, Soft IP

AHB system Peripheral IP, AHB - to - APB Bridge, Soft IP

AHB system Peripheral IP, External Bus controller, Soft IP

AHB system Peripheral IP, SRAM/ROM Controller, Soft IP

AHB system Peripheral IP, AHB - to - AHB Bridge, Soft IP

AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP

AHB system Peripheral IP, Interrupt controller, Soft IP

AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP

Interface Controller - PHY IP->AMBA AHB / APB/ AXI->AMBA AXI (7)

AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP

AXI Bus Controller IP, Bus Controller, Soft IP

AXI system Peripheral IP, AXI/APB host bridge, Soft IP

AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP

AXI system Peripheral IP, AXI to AXI Bridge, Soft IP

AXI system Peripheral IP, Interrupt Controller, Soft IP

AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP

Interface Controller - PHY IP->MIPI->MIPI Controller (4)

MIPI Controller IP, CSI-2 Receiver, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP

MIPI Controller IP, DSI Host, Soft IP

MIPI Controller IP, DSI Peripheral, Soft IP

MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP

Interface Controller - PHY IP->MIPI->MIPI PHY (30)

MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process

MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process

MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process

MIPI D-PHY Transmitter IP, 80Mbps - 1Gbps, UMC 40nm LP process

MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 55nm SP process

MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 55nm SP process

MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI M-PHY IP, UMC 40nm LP process

MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process

MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process

MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process

MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process

MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process

MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process

MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process

MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process

MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC process

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process

MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process

MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process_x005F_x005F_x005F_x005F_x005F_x000D_

MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process

MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process

MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process

MIPI On-Die Termination ; UMC 28nm HPC process

Interface Controller - PHY IP->Multi-Protocol PHY-> (1)

16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+

Interface Controller - PHY IP->Other-> (3)

CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process

28nm HPC x4 lane 10 Gbps SERDES

Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process

Interface Controller - PHY IP->PCI->PCI Controller (1)

PCI-X Controller IP, PCIX 1.0b, Soft IP

Interface Controller - PHY IP->PCI->PCI Express (4)

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process

PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.

PCIe Gen4 x8 Lane Endpoint Controller

The PCIe Gen3 PCS for 28nm programmable serdes.

Interface Controller - PHY IP->PCI->PCI Express Phy (7)

PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP

PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process

PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process

Interface Controller - PHY IP->SATA-> (6)

SATA III PHY IP, Gen-3, UMC 0.11um HS/FSG process

SATA III PHY IP, Gen-3, UMC 55nm SP process

SATA II PHY IP, UMC 55nm SP process

UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES

UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES

28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process

Interface Controller - PHY IP->SATA->SATA Controller (2)

SATA Controller IP, SATA Gen-3 Host, Soft IP

SATA Controller IP, SATA Gen-3, Soft IP

Interface Controller - PHY IP->SATA->SATA PHY (6)

SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process

SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process

SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process

SATA II PHY IP, Gen-2, UMC 0.11um HS/AE process

SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process

SATA II PHY IP, Gen-2, UMC 90nm SP process

Interface Controller - PHY IP->USB-> (2)

ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process

USB Type-C and Power deliver Controller

Interface Controller - PHY IP->USB->USB 3.0 (28)

USB 1.1 PHY IP, UMC 0.13um LL/FSG process

USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 0.11um HS/AE process

USB 1.1 PHY IP, UMC 0.18um G2 process

USB 1.1 PHY IP, UMC 0.18um G2 process

USB 2.0 Device PHY IP, Non-Crystal mode support, HJTC 0.11um pFlash/LL process

USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process

USB 2.0 Device PHY IP, UMC 0.13um LL/FSG process

USB 2.0 Device PHY IP, UMC 0.18um G2 process

USB 2.0 Device PHY IP, UMC 0.18um G2 process

USB 3.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process

USB 3.0 OTG PHY IP, UMC 40nm LP process

USB 2.0 Device PHY IP, UMC 0.11um eFlash process

USB 1.1 PHY IP, UMC 0.5um Logic process

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process

USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process

USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process

USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF

USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process

USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process

USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process

Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.

USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process

USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process

USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x005F_x005F_x005F_x005F_x000D_ cost down from FZOTG266HJ0C_A

USB 2.0 On-The-Go PHY; UMC 28nm HLP Process

USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function

Interface Controller - PHY IP->USB->USB 3.0 PHY (5)

USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process

USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process

USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process

USB 3.0 OTG PHY IP, UMC 55nm SP process

USB 3.0 OTG PHY IP, UMC 90nm SP process

Interface Controller - PHY IP->USB->USB 3.1 (2)

28nm HPC USB3.1 gen2 PHY(10Gbps)

28nm HPC+ USB3.1 gen2 PHY(10Gbps)

Interface Controller - PHY IP->USB->USB Controller (2)

USB 1.1 Device Controller IP, Soft IP

USB 2.0 Device Controller IP, Device controller, Soft IP

Interface Controller - PHY IP->USB->USB On-The-Go (9)

USB 1.1.OTG PHY IP, OTG, UMC 0.11um HS/AE process

USB 2.0 OTG PHY IP, UMC 55nm LP process

USB 1.1.OTG PHY IP, HJTC 0.18um eFlash/G2 process

USB 1.1.OTG PHY IP, UMC 0.13um HS/FSG process

USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process

USB 2.0 OTG PHY IP, UMC 0.18um G2 process

USB 2.0 OTG PHY IP, UMC 0.25um process

USB 2.0 OTG PHY IP, UMC 40nm LP process

USB 2.0 OTG PHY IP, UMC 55nm eFlash process

Interface Controller - PHY IP->USB->USB On-The-Go PHY (25)

USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process

USB 1.1.OTG PHY IP, OTG, UMC 0.13um SP/FSG process

USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process

USB 1.1.OTG PHY IP, OTG, UMC 0.15um SP process

USB 1.1.OTG PHY IP, OTG, UMC 0.25um Logic process

USB 2.0 OTG PHY IP, UMC 0.13um LL/FSG process

USB 2.0 OTG Controller IP, Support On-The-Go (Level 3), Soft IP

USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process

USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process

USB 1.1.OTG PHY IP, UMC 0.11um HS/FSG process

USB 1.1.OTG PHY IP, OTG, UMC 0.18um eFlash/G2 process

USB 1.1.OTG PHY IP, OTG, UMC 65nm LL process

USB 1.1.OTG PHY IP, UMC 90nm LL process

USB 2.0 OTG PHY IP, UMC 0.11um HS/AE process

USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/AE process

USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/FSG process

USB 2.0 OTG PHY IP, OTG, UMC 0.153um Logic process

USB 2.0 OTG PHY IP, UMC 0.18um eFlash/G2 process

USB 2.0 OTG PHY IP, UMC 0.18um eFlash/G2 process

USB 2.0 OTG PHY IP, UMC 55nm SP process

USB 2.0 OTG PHY IP, UMC 65nm SP process

USB 2.0 OTG PHY IP, UMC 65nm LL process

USB 2.0 OTG PHY IP, UMC 65nm LP process

USB 2.0 OTG PHY IP, UMC 90nm SP process

USB 2.0 OTG PHY IP, UMC 90nm LL process

Interface Controller - PHY IP->USB->USB Phy (10)

USB 1.1 PHY IP, UMC 0.13um HS/FSG process

USB 1.1 PHY IP, UMC 0.15um SP process

USB 1.1 PHY IP, UMC 0.18um eFlash/G2 process

USB 1.1 PHY IP, UMC 65nm SP process

USB 2.0 Device PHY IP, UMC 0.11um HS/AE process

USB 2.0 Device PHY IP, UMC 0.11um HS/FSG process

USB 2.0 Device PHY IP, UMC 0.11um LL/FSG process

USB 2.0 Device PHY IP, UMC 0.13um CIS process

USB 2.0 Device PHY IP, UMC 0.18um G2 process

USB 2.0 Device PHY IP, UMC 0.18um CIS process

Interface Controller - PHY IP->V-by-One-> (6)

Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.

V-by-One Receiver

V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller).

Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output finally.

V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller).

FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream

Memory Controller - PHY IP->DDR-> (90)

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device

DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process.

compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process .

DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process

UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device

40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage

40nm LPDDR2-PHY command/address block for SIP

40nm LPDDR2-PHY data block for SIP

LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process

40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

DDR3 RTL PHY Address Command module

DDR3 RTL PHY data module

Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces

DDRx Bist Controller with I2C slave and multi-channel AMBA master

DFI Wrapper

Memory Controller - PHY IP->DDR->DDR PHY (1)

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

Memory Controller - PHY IP->Flash Controller-> (2)

Flash Memory Controller IP, Support page sizes of 512, 2K, 4K, 8K and 16K bytes NAND Flash memory, 74bit ECC correction (512 or 1K bytes sectors), Soft IP

Flash Memory Controller IP, Support NAND type Flash memory of 8MB - 2 GB, 24 ECC bits per 512 bytes, Soft IP

Memory Controller - PHY IP->NAND Flash->NAND Flash Controller (2)

Memory Controller IP, Memory Stick controller, Soft IP

Memory Controller IP, NAND Flash memory Host controller, Soft IP

Memory Controller - PHY IP->ONFI Controller-> (1)

ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process

Memory Controller - PHY IP->Other-> (8)

Controller IP, System Power/Clock Management, Soft IP

DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY

Embedded flash controller

Flash Memory pre-fetcher controller with AHB lite system

Embedded flash controller for UMC 55LP Spit Gate embedded Flash.

Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.

DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP

Controller IP, SPI Flash controller, Soft IP

Memory Controller - PHY IP->SD->SD Controller (3)

Compact Flash host interface controller with APB interface.

Secure digital card host controller with APB interface.

SD Host Controller IP, SD host spec. v3.0, SDIO spec. v2.0, MMC spec. v4.3, Supports UHS50/UHS104 card, Soft IP

Memory Controller - PHY IP->SDRAM Controller-> (103)

Single Port SRAM Compiler IP, UMC 0.11um HS/AE process

Single Port SRAM Compiler IP, UMC 0.11um LL/AE process

Single Port SRAM Compiler IP, UMC 0.11um LL process

Single Port SRAM Compiler IP, UMC 0.11um SP/AE process

Single Port SRAM Compiler IP, UMC 0.11um HV process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous, UMC 0.18um eFlash/G2 process

Single Port SRAM Compiler IP, 4.0um2 bit cells, High density, Low Power, UMC 0.18um LL process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 55nm CIS process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process

Single Port SRAM Compiler IP, UMC 55nm LP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, HVT, Support Repair Features, UMC 55nm CIS process

Single Port SRAM Compiler IP, UMC 55nm eHV process

Single Port SRAM Compiler IP, UMC 55nm eHV process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 80nm HV process

Single Port SRAM Compiler IP, Support Repair Features, UMC 80nm HV process

Single Port SRAM Compiler IP, UMC 90nm LL process

Single Port SRAM Compiler IP, UMC 90nm CIS process

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm CIS process

Single Port SRAM Compiler IP, High density, UMC 0.13um HS/FSG process

Single Port SRAM Compiler IP, UMC 0.11um eFlash/HS process

Single Port SRAM Compiler IP, UMC 0.11um HS/AE process

Single Port SRAM Compiler IP, UMC 0.11um HS/AE process

Single Port SRAM Compiler IP, UMC 0.11um HS/FSG process

Single Port SRAM Compiler IP, UMC 0.11um HS/FSG process

Single Port SRAM Compiler IP, UMC 0.11um LL process

Single Port SRAM Compiler IP, UMC 0.11um SP process

Single Port SRAM Compiler IP, UMC 0.13um HS/FSG process

Single Port SRAM Compiler IP, UMC 0.13um LL process

Single Port SRAM Compiler IP, UMC 0.13um SP process

Single Port SRAM Compiler IP, 4.0um2 bit cells, High density, Low Power, UMC 0.18um G2 process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high speed , UMC 0.18um G2 process

Single Port SRAM Compiler IP, UMC 0.25um process

Single Port SRAM Compiler IP, UMC 0.25um process

Single Port SRAM Compiler IP, UMC 0.25um process

Single Port SRAM Compiler IP, UMC 0.25um process

Single Port SRAM Compiler IP, UMC 0.25um process

Single Port SRAM Compiler IP, UMC 0.25um SP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 28nm HLP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 40nm LP process

Single Port SRAM Compiler IP, UMC 55nm eFlash process

Single Port SRAM Compiler IP, UMC 55nm eFlash process

Single Port SRAM Compiler IP, UMC 55nm LP process

Single Port SRAM Compiler IP, UMC 55nm LP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 90nm SP process

Single Port SRAM Compiler IP, UMC 90nm SP process

Single Port SRAM Compiler IP, UMC 90nm SP process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um LL process

Single Port SRAM Compiler IP, UMC 0.15um SP process

Single Port SRAM Compiler IP, UMC 0.13um SP/FSG process

Single Port SRAM Compiler IP, UMC 0.13um HS/FSG process

Single Port SRAM Compiler IP, UMC 0.13um CIS process

Single Port SRAM Compiler IP, UMC 0.15um SP process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process

Single Port SRAM Compiler IP, UMC 90nm LL process

Single Port SRAM Compiler IP, UMC 65nm SP process

Single Port SRAM Compiler IP, UMC 90nm SP process

Single Port SRAM Compiler IP, UMC 0.162um G2 process

Single Port SRAM Compiler IP, 5.6um2 bit cells, Synchronous, UMC 0.18um eFlash/G2 process

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process

Single Port SRAM Compiler IP, UMC 0.11um LL/AE process

Single Port SRAM Compiler IP, UMC 0.11um SP/AE process

Single Port SRAM Compiler IP, UMC 0.153um MS process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um CIS process

Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um MS process

Single Port SRAM Compiler IP, UMC 0.25um Logic process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 55nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process

Single Port SRAM Compiler IP, UMC 65nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process

Single Port SRAM Compiler IP, UMC 65nm LL process

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process

Single Port SRAM Compiler IP, UMC 90nm LL process

Memory Controller - PHY IP->SRAM Controller-> (1)

SRAM/ROM Controller IP, SRAM/ROM Controller, Soft IP

Wireline Communication IP->Ethernet-> (9)

10/100 Ethernet PHY IP, UMC 90nm SP process

10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process

10/100 Ethernet PHY IP, UMC 0.18um MS process

10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process

0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process

Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.

10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_

Wireline Communication IP->Ethernet->10Base-T/100Base-TX (1)

10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process

Wireline Communication IP->Ethernet->11Base-T/100Base-TX (1)

10/100 Ethernet PHY IP, UMC 65nm SP process

Wireline Communication IP->Ethernet->15Base-T/100Base-TX/1000Base-T (1)

10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process

Wireline Communication IP->Ethernet->Ethernet MAC (2)

Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP

Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP