Design & Reuse
Digital Blocks, Inc.
Corporate Headquarters
Digital Blocks, Inc.
Glen Rock, 07452
USA

About Digital Blocks, Inc.

Digital Blocks architects, designs, verifies, and markets semiconductor Intellectually Property (IP) cores to worldwide technology systems companies. The company's expertise is in Embedded Processor & Peripherals, Display Controller, Display Link Layer, 2D Graphics, Image Compression, Audio / Video Processing, and High-Speed Networking / A/V Networking & Routing / High-Frequency Trading Networking.
Analog & Mixed Signal->Graphics & Video Modules-> (1)
FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
Graphic - Peripheral IP->DMA Controller-> (3)
AMBA Parameter Configurable Multi-Channel DMA Controller (typically 1 to 256)
AHB Multi-Channel DMA Controller
AXI4 Multi-Channel DMA Controller (fixed 2,4,8,16 DMA Channels)
Graphic - Peripheral IP->Input/Output Controller-> (1)
Programmable Peripheral Interface
Graphic - Peripheral IP->Interrupt Controller-> (2)
Programmable Interrupt Controller
Programmable Interrupt Controller (Synchronous)
Graphic - Peripheral IP->Keyboard Controller-> (1)
Programmable Keyboard / Display Interface
Graphic - Peripheral IP->LCD Controller-> (4)
Display Controller - LCD / OLED Panels (AXI Bus)
Display Controller - LCD / OLED Panels (AXI4 Bus)
Display Controller - LCD 4K Digital Cinema (DCI)
AXI Bus Display Controller
Interconnect, D2D, C2C->Intra SoC Connectivity-> (1)
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
Display Controller - LCD / OLED Panels (AHB Bus)
RGB to CCIR 601 / 656 Encoder
BitBLT Graphics Hardware Accelerator (AXI Bus)
BitBLT Graphics Hardware Accelerator (AHB Bus)
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
eSPI & SPI Master Controller w/FIFO
eSPI & SPI Slave Controller w/FIFO
RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing
RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO
SPI Master / Slave Controller w/FIFO (APB Bus)
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
Display Controller - LCD / OLED Panels (AHB-Lite Bus)
2D Graphics Hardware Accelerator (AXI4 Bus)
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
SPI Master Controller w/FIFO (APB Bus)
UDP/IP Hardware Protocol Stack - 100G
I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
I3C Master / Slave Controller w/FIFO (APB Bus)
I3C Master Controller w/FIFO (APB Bus)
I3C Slave Controller w/FIFO (APB Bus)
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
UDP/IP Hardware Protocol Stack - 50G
UDP/IP Hardware Protocol Stack - 40G
UDP/IP Hardware Protocol Stack - 25G
UDP/IP Hardware Protocol Stack - 10G
UDP/IP Hardware Protocol Stack - 1G
I3C Master / Slave Controller - MIPI Basic v1.0
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
I2C Slave with APB Master Bridge (I2C2APB)
I2C Slave with AXI Master Bridge (I2C2AXI4)
I2C Slave with AHB Master Bridge (I2C2AHB)
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
Interface Controller - PHY IP->I2C-> (14)
I2C Master Controller w/FIFO (APB Bus)
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
I2C Master / Slave Controller w/FIFO (APB Bus)
I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)
I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
I2C Slave Controller - Low Power, Low Noise Config of User Registers
I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
I2C Slave Controller - Low Power, Low Noise Config with APB Interface
I2C Slave Controller w/FIFO (AXI Bus)
I2C Slave Controller w/FIFO (APB Bus)
I2C Slave Controller w/FIFO (AHB Bus)
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