701 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

702 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

703 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

704 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

705 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

706 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

707 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

708 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

709 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

710 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

711 3.0

MIPI 4.1 M-PHY HS Gear 4 MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...

712 3.0

High Performance, Low Latency PCIe Gen5 PHY Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high i...

713 3.0

MIPI PHY This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...

714 3.0

MIPI D-PHY NEC 90nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

715 3.0

MIPI M-PHY Designed For GF 28nm ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...

716 3.0

UHS-II PHY for SD4/SD5 TSMC 16nm FF SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

717 3.0

UHS-II PHY for SD4/SD5 TSMC 12nm FF SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

718 3.0

USB 2.0 (LS, FS & HS) On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...

719 3.0

Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain, SPI in TSMC 110nm This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this nod...

720 3.0

<4Gbps Low Power D2D Interface Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...

721 3.0

TSMC 22nm ULL Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO and 1.8V Analog Cell This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. Th...

722 3.0

TSMC 22nm ULL Wirebond/Flipchip I/O Library with switchable 1.8V/3.3V GPIO, 3.3V I2C ODIO, and 3.3V Analog Cell This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V durin...

723 3.0

Three-Speed Inline I/O Library with ODIO in TSMC 22nm This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. A...

724 3.0

1.8V/3.3V flipchip I/O library with 4kV HBM ESD protection, I2C compliant ODIO This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...

725 3.0

A Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD pro...

726 3.0

1.8V/3.3V Flipchip I/O Library with 4kV HBM, I2C Compliant ODIO and 5V Hot-Plug Detect This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...

727 3.0

1.8V/3.3V Fail-Safe Multi-Voltage GPIO This silicon-proven TSMC 28nm Digital I/O Library delivers a high-performance, low-power interface solution designed for advanced digital applications...

728 3.0

A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions. This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and...

729 3.0

Inline Wirebond 1.8V to 3.3V Multi-Voltage GPIO with 5V Open-Drain I/O This I/O Libraru is a high-performance I/O solution for TSMC 22nm technology, supporting both digital and analog interfaces. Designed for 1.8V3.3V ope...

730 3.0

I2C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

731 3.0

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...

732 3.0

I2C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...

733 3.0

Configurable AES Core eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a...

734 3.0

Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

735 3.0

USB 3.0 Device ...

736 3.0

MIPI SPMI Slave IP MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through i...

737 3.0

MIPI RFFE Master IP MIPI RFFE Master interface provides full support for the two-wire MIPI RFFE synchronous serial interface, compatible with RFFE specification. Through ...

738 3.0

Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bu...

739 3.0

I2C Slave Controller - Low Power, Low Noise Config of User Registers The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of r...

740 3.0

2D Graphics Hardware Accelerator (AXI4 Bus) The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB9200...

741 3.0

I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus) The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or othe...

742 3.0

Controlled Impedance Multi-Protocol I/O Library featuring three I/O cells This I/O library is a high-performance GPIO solution designed for the TSMC FFC/FCC+ process. This flipchip compatible library provides a robust and fl...

743 3.0

I2C Slave with APB Master Bridge (I2C2APB) The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

744 3.0

I2C Slave with AXI Master Bridge (I2C2AXI4) The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

745 3.0

I2C Slave with AHB Master Bridge (I2C2AHB) The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

746 3.0

A TSMC 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options A key attribute of the Certus 28nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operatio...

747 3.0

1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in TSMC 22nm A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO ce...

748 2.0

SATA Host 6G Controller on Kintex 7 The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...

749 2.0

SATA 3 Host Controller on ZYNQ The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...

750 2.0

SATA Device Controller on Kintex 7 The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...