101 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

102 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

103 50.0

TSMC 3nm (N3E) 1.5V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

104 50.0

TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

105 50.0

TSMC 3nm (N3E) GPIO Basekit Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

106 50.0

USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

107 50.0

USB-C 3.2 DP/TX PHY in TSMC (N3E) The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...

108 50.0

MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

109 50.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

110 50.0

MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

111 50.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5, N3E, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

112 50.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

113 50.0

MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...

114 50.0

32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P) The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...

115 50.0

USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

116 50.0

USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E) The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...

117 50.0

56G Ethernet PHY in TSMC (16nm, 12nm) The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...

118 50.0

32G Multi Rate SerDes PHY - GlobalFoundries 22FDX Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

119 50.0

PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P) The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

120 50.0

PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P) The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

121 45.0

32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

122 45.0

32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

123 45.0

MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G The MXL-MIPI-M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used ...

124 45.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps The MXL-CDPHY-4p5G-CSI-2-TX+-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifica...

125 45.0

FlexNoC 5 Network-on-Chip (NoC) Arteris FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of sy...

126 45.0

MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP The MXL-D-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

127 40.0

MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...

128 40.0

MIPI RFFE Master Controller IP Core v3.0 Mobile radio communication systems are complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE standard v3.0...

129 40.0

MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense. To accommodate a range of applications, users can config...

130 40.0

MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI The MXL-DPHY-CSI-2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. T...

131 40.0

USB 2.0 PHY The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

132 40.0

Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane * The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8...

133 40.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

134 40.0

RapidIO Controller with V4.1 Support Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host...

135 40.0

PCIe Gen6 Controller Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system communication, suppo...

136 40.0

DP/eDP1.4b RX PHY Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

137 40.0

DP/eDP1.4b TX PHY Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

138 38.0

UCIe Die-to-Die Controller GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UC...

139 38.0

PCIe 6.x / PCIe5.x / PCIe4.x / PCIe3.x / PCIe2.x / PCIe1.x Controller The Controller IP is customer configurable and supports PCIe 6.x/PCIe5.x/PCIe4.x/PCIe3.x/ PCIe2.x/PCIe1.x Specifications. The Controller IP support la...

140 38.0

Compute Express Link (CXL) 1.1/2.0/3.0 Controller The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CX...

141 38.0

1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS) The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY. It is a highly configurable IP that supp...

142 38.0

1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Expres...

143 38.0

Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) The ZeusCORE Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave IP product portfolio. It is a hig...

144 35.0

MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+ The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting c...

145 35.0

VESA VDC-M V1.2 Decoder Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Decoder. Our groundbreaking product revolutionizes video compression technology, off...

146 35.0

MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification f...

147 33.0

Ultra Low-Latency IP PCI-express Framework LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those in the financial secto...

148 30.0

PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...

149 30.0

MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM The MXL-DPHY-CSI-2-RX+ is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY...

150 30.0

Universal Chiplet Interconnect Express (UCIe) Controller Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...