1651 0.0

UCIE 1.0 Support for multiple protocol PCIE/CXL/Streaming...

1652 0.0

PCIE Gen7 Controller Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....

1653 0.0

PCIe 6.2 Switch IP Controller ...

1654 0.0

MIPI D-PHY TRx(80-2500Mbps) 14nm The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1655 0.0

MIPI D-PHY TRx(80-2500Mbps) 28nm The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1656 0.0

DSC 1.2b Encoder The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...

1657 0.0

DSC 1.2b Decoder The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...

1658 0.0

MIPI CSI-2 RX Controller The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...

1659 0.0

MIPI DSI-2 TX Controller The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...

1660 0.0

AXI to APB Bus Bridge The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...

1661 0.0

MIPI C-PHY TRx(80-8000Msps) 5nm The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...

1662 0.0

PCIe refclk buffer on 14nm The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...

1663 0.0

PCIe refclk buffer on 8nm The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...

1664 0.0

PCIe 6.0 PHY on 4nm The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...

1665 0.0

PCIe 4.0 PHY on 8nm The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...

1666 0.0

eDP v1.5a RX PHY 14nm The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...

1667 0.0

MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY 4nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...

1668 0.0

MIPI D-PHY TRx(80-4500Mbps) 8nm The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1669 0.0

MIPI D-PHY TRx(80-4500Mbps) 5nm The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1670 0.0

MIPI D-PHY TRx(80-2500Mbps) 14nm The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1671 0.0

AXI External Memory Controller The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (SRAM, Flash, etc.). Th...

1672 0.0

MIPI D-PHY TRx(80-2500Mbps) 14nm The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1673 0.0

MIPI D-PHY TRx(80-2500Mbps) 11nm The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1674 0.0

MIPI D-PHY TRx(80-2100Mbps) 14nm The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1675 0.0

MIPI D-PHY TRx(80-2100Mbps) 14nm The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1676 0.0

MIPI D-PHY TRx(80-2150Mbps) 28nm The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...

1677 0.0

MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 8nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

1678 0.0

MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 4nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

1679 0.0

UCIe 1.1 PHY 5nm The UCI Express Specification Revision 1.1 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

1680 0.0

UCIe 2.0 PHY 4nm The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...

1681 0.0

MIPI Testbench Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design. This includes the follow features: • Separ...

1682 0.0

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...

1683 0.0

PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root po...

1684 0.0

ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...

1685 0.0

AHB Channel with Decoder and Data Mux The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...

1686 0.0

APB Channel with Decoder and Data Mux The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...

1687 0.0

SPI Slave to AHB Lite Master The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...

1688 0.0

AHB Single Channel DMA Controller The DMA is a configurable single channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured...

1689 0.0

AMBA AHB 4 Channel DMA Controller The DMA is a multiple-channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and F...

1690 0.0

AHB to APB Bus Bridge The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction. This is accomplished via two small state machines ...

1691 0.0

AHB External Bus Interface The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an ext...

1692 0.0

AHB Triple DES with DMA The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypt...

1693 0.0

Small area rail clamp for FinFET Power clamp ESD solutions Rail clamp ESD protection 0.75V domain Small area...

1694 0.0

SPI Slave to AXI Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1695 0.0

AHB Lite to SPI Bridge The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...

1696 0.0

AHB Performance Subsystem - ARM M0 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...

1697 0.0

AHB AES with DMA The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...

1698 0.0

AHB-Lite to AHB-Lite Asynchronous Bridge The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...

1699 0.0

Secure AHB Performance Subsystem - ARM M3 The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It in...

1700 0.0

XSR PHY for TSMC N5 The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...