1701 0.0

I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs interfacing to user registers while autonomous i...

1702 0.0

Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus...

1703 0.0

Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO The Digital Blocks DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or an...

1704 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N7, N5A, N3A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1705 0.0

MIPI D-PHY v1.2 RX 2 Lanes in Samsung (8nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1706 0.0

MIPI D-PHY v1.2 TX 4 Lanes in Samsung (8nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1707 0.0

PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...

1708 0.0

UCIe Controller for Streaming Protocols Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

1709 0.0

SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...

1710 0.0

PCIe 6.0 PHY NCS IP for TSMC (N3E, N3P) The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

1711 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1712 0.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N5) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1713 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1714 0.0

UCIe-S PHY for Standard Package (x32) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1715 0.0

PCIe 3.0 PHY in Samsung (SF5A The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

1716 0.0

UCIe PHY IP on TSMC N3P Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1717 0.0

SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...

1718 0.0

PCIe 6.0 PHY IP for TSMC N5 The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

1719 0.0

USB4 PHY - SS SF2, North/South Poly Orientation The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...

1720 0.0

28G Ethernet PHY IP for TSMC N7 The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...

1721 0.0

PCIe 5.0 PHY for TSMC N3P The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

1722 0.0

PCIe 5.0 PHY for TSMC N7 The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

1723 0.0

USB4 PHY IP for TSMC N3E The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...

1724 0.0

Synopsys PCIe 4.0 PHY IP for TSMC N7 The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

1725 0.0

Multiprotocol 10G PHY in Samsung (8nm) The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...

1726 0.0

Multiprotocol 10G PHY in TSMC (16nm, N7) The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...

1727 0.0

112G VSR PHY in TSMC (N5, N3P) Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...

1728 0.0

112G PHY in TSMC (N7, N5) Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...

1729 0.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1730 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1731 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1732 0.0

eUSB 2.0 PHY in TSMC (N3A) for Automotive Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...

1733 0.0

HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF5A) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

1734 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1735 0.0

MIPI D-PHY Rx-Only 2 Lanes in Samsung (8nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1736 0.0

MIPI D-PHY Rx-Only 4 Lanes in Samsung (8nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1737 0.0

MIPI D-PHY Tx-Only 2 Lanes in Samsung (8nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1738 0.0

MIPI M-PHY Type 1 G5 2TX2RX in TSMC (N4P, N3E) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

1739 0.0

MIPI M-PHY Type 1 G5 2TX2RX, SR in TSMC (N3P) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

1740 0.0

PCIe 3.0 PHY in TSMC (28nm, 12nm, N4P) The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

1741 0.0

PCIe 5.0 PHY in GlobalFoundries (12nm) The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

1742 0.0

USB-C 3.2 DP/TX PHY AR in TSMC (N3P) The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...

1743 0.0

Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7 Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

1744 0.0

Synopsys MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes for TSMC N5 Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1745 0.0

Synopsys 32G PHY NCS for TSMC N5 The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and c...

1746 0.0

Synopsys PCIe 6.0 PHY IP for TSMC N4P The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...

1747 0.0

SPI Master Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...

1748 0.0

SPI Master Controller w/FIFO (APB Bus) The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...

1749 0.0

I2C Slave Controller - Low Power, Low Noise Config with APB Interface The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA...

1750 0.0

I2C Slave Controller w/FIFO (AXI Bus) The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI...