351 15.0

DP/eDP1.4b TX Controller Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....

352 15.0

120dB PDM-to-PCM Digital Microphone Interface The AR36T05 is a soft macro low-power high-performance digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modu...

353 15.0

Interlaken Controller Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...

354 15.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

355 14.0

MIPI DSI TX Controller DSI transmitter controller for application The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance Specificatio...

356 14.0

Dual-Role Device Controller for USB 3.1 Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...

357 14.0

USB 2.0 Controller Mature controller solution for OTG and Device applications Certified for compliance with Universal Serial Bus Specification, Revision 2.0, the Cadenc...

358 14.0

USB 3.1 Device Controller Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...

359 14.0

MIPI CSI-2 RX Controller for v2.1 CSI-2 receiver controller for application processor The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is respons...

360 14.0

PCI Express (PCIe) 2.1 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding desi...

361 14.0

USB 3.0 xHCI Host Controller Mature solutions featuring xHCI Host, Device, and Dual-Role Device Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 and xHCI Speci...

362 14.0

Controller for MIPI Soundwire Audio data transport The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required...

363 14.0

10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flex...

364 14.0

CXL Controller Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Cadence® Controller IP for CXL provides the logic r...

365 14.0

10Gbps Multi-Protocol PHY IP Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The PHY IP is designed to deliver high eye-margin at low power for backp...

366 14.0

Dual-Role Device Controller for USB 3.0 Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.0 Specification v1.0, and xHCI Specification v1.0, th...

367 14.0

MIPI CSI-2 TX Controller for v2.1 CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance ...

368 14.0

I3C Controller Controller IP for the MIPI I3C interface The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high ...

369 14.0

MIPI D-PHY for TSMC D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, ...

370 14.0

PCI Express (PCIe) 5.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a roo...

371 14.0

PCI Express (PCIe) 4.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a roo...

372 14.0

PCI Express (PCIe) 3.1 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 3.1 is a solution created for mobile applications...

373 14.0

USB 2.0 PHY for TSMC Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...

374 14.0

40G Ultralink D2D PHY for Samsung 7LPP Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

375 14.0

40G Ultralink D2D PHY for GF12LP+ Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

376 14.0

UltraLink Controller Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...

377 14.0

Universal Chiplet Interconnect Express (UCIe 1.0) Controller Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...

378 14.0

USB2.0 OTG PHY supporting UTMI+ level 3 interface - 40LL / 110G / 130G / 130EF The USB2.0 OTG PHY is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design usage. The USB2.0 O...

379 14.0

Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel This 12.5Gbps SERDES IP is designed for smooth integration of Multiple SERDES lanes offering best in class performance, area and power. The programmab...

380 14.0

USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL The USB2.0 OTG PHY is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design usage. The USB2.0 O...

381 13.0

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...

382 13.0

VESA VDC-M Decoder The Video Electronics Standards Association (VESA®) introduced the VESA Display Compression-M (VDC-M) standard, a new display interface compression st...

383 12.0

USB 2.0 Device Transceiver PHY ...

384 12.0

PCI Express PHY serial link PIPE Transceiver IP cell/hard macro SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...

385 12.0

Serial ATA (SATA) I/II PHY IP CORE SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...

386 12.0

105dB PCM-to-PDM Stereo Converter The AR37T01 is a digitally coded stereo PCM-to-PDM conversion IP with 8-bit pattern-code programming. The IP translates parallel PCM input data in...

387 11.0

Die-to-Die (D2D) Interconnect Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...

388 11.0

MIPI D-PHY ...

389 11.0

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...

390 11.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...

391 11.0

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...

392 11.0

I2S/Left-Justified/TDM Digital Audio Interface The AR38U12 is a soft macro IP supporting industry-standard I2S, Left-Justified and Time-Division-Multiplexed (TDM) serial interface to parallel PCM (...

393 10.0

DisplayPort TX IP for high-bandwidth applications (12nm, 16nm, 28nm) M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...

394 10.0

UFSHCI 4.0 The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...

395 10.0

MIPI CSI-2 Receiver for FPGA MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor....

396 10.0

MIPI CSI-2 Transmitter for FPGA MIPI CSI-2 Tx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processer...

397 10.0

MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY MIPI is the Mobile Industry Processor Interface that provides specification for software and hardware interfaces in mobile terminals and thereby encou...

398 10.0

SD 4.1 SDIO 4.1 Host Controller IP The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...

399 10.0

PCI Express - Configurable PCI Express 4.0 IP The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functi...

400 10.0

MIPI D-PHY Receiver for TSMC 40nm LP The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process....